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path: root/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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2019-06-19arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASEPriyanka Jain
As per hardware documentation, CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-12-06armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-04move data structure out of cpu.hYork Sun
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFCSriram Dash
IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl-layerscape: Fix final MMU table for QSPI and IFCSuresh Gupta
For QSPI and IFC addresses execution shouldn't be allowed when u-boot running from DDR. Revise the MMU final table to enforce execute-never bits. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Drop macro CONFIG_LS2080AYork Sun
Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Update early MMU for DDR after initializationYork Sun
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-18ARMv8/fsl-layerscape: Correct the OCRAM sizeHou Zhiqiang
The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu
The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-19armv8: layerscape: Convert to use common MMU frameworkYork Sun
Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-28armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Enable QSPI boot supportYuan Yao
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06armv8: LSCH2 early and final mmu needs matching NS attributeEd Swarthout
When switching between the early and final mmu tables, the stack will get corrupted if the Non-Secure attribute is different. For ls1043a, this issue is currently masked because flush_dcache_all is called before the switch when CONFIG_SYS_DPAA_FMAN is defined. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29armv8: fsl-layerscape: Add LS1023A SVRMingkai Hu
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-15arm64: Remove non-full-va map codeAlexander Graf
By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-01-27armv8/ls1043aqds: add QSPI boot supportQianyu Gong
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25armv8: ls2040a: Add support of LS2040A SoCPratiyush Mohan Srivastava
Freescale's LS2040A is a another personality of LS2080A SoC without AIOP support consisting of 4 armv8 cores. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2015-12-15armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: fsl-layerscape: Fix early MMU table for nand bootYork Sun
The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-30armv8/layerscape: Update MMU table with execute-never bitsAlison Wang
For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
2015-11-30armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha
Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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