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path: root/arch/arm/include/asm/arch-mx6/imx-regs.h
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2015-06-27imx: mx6 introuduce macro is_mx6dqpPeng Fan
Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-26arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher
add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
2015-05-19mx6: add OTP bank1 registersTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-03-02imx6: Added DEK blob generator commandRaul Cardenas
Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
2015-02-10imx: mx6: Fixed AIPS3 base address issueYe.Li
Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
2015-02-10imx:mx6 update fuse_bank0_regsPeng Fan
Update fuse_bank0_regs structure according reference mannual. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-12-31arm:mx6sx add QSPI supportPeng Fan
Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-20mx6: add weim registersFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-29usb: ehci-mx6: Rename the USB register base addressYe.Li
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-09mx6: imx-regs: Provide a structure for GPC registersFabio Estevam
Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20mx6: add support of multi-processor commandGabriel Huau
This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-08mx6: imx-regs: Remove unused 'omux' field from iomux structFabio Estevam
'omux' field is not used anywhere and such layout is not valid for mx6solox. Instead of adding more ifdef's into the structure, let's simply remove this unused 'omux' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23i.MX6: add enable_spi_clk()Heiko Schocher
add enable_spi_clk(), so board code can enable spi clocks. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
2014-07-23i.MX6: define struct pwm_regs and PWMCR_* definesHeiko Schocher
add defines for pwm modul found on imx6. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2014-07-23imx6: add gpr2 usb_otg_id iomux select control defineHeiko Schocher
add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK define for the USB_OTG_ID_SEL bit. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23mx6: Adjust the GPR offset for mx6soloxFabio Estevam
On mx6solox there is an additional 0x4000 offset for the GPR registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23mx6: Remove duplication of iomuxc structureFabio Estevam
There is no need to keep iomuxc_base_regs structure as it serves the exact same purpose of the iomuxc structure, which is to provide access to the GPR registers. The additional fields of iomuxc_base_regs are not used. Other advantage of 'iomuxc' is that it has a shorter name and the variable declarations can fit into a single line. So remove iomuxc_base_regs structure and use iomuxc instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-10mx6: Add support for the mx6solox variantFabio Estevam
mx6solox is the newest member of the mx6 family. Some of the new features on this variants are: - Cortex M4 microcontroller (besides the CortexA9) - Dual Gigabit Ethernet Add the initial support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-06-17imx: correct HAB status for new chip TOStefano Babic
According to: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0 ENGR00287268 mx6: fix the secure boot issue on the new tapout chip commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b newer i.MX6 silicon revisions have an updated ROM and HAB API table. Please see also: i.MX Applications Processors Documentation Engineering Bulletins EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison With this change the secure boot status is correctly displayed Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-02-21Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2014-02-18spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controllerMarkus Niebel
The dual lite and solo variant have only 4 SPI controller. respect this in the MXC_SPI_BASE_ADRESSES macro Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18spi: spi-mxc: add defines for clk inactive state for ECSPIMarkus Niebel
Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-11mx6: Enable L2 cache supportFabio Estevam
Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-17mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-15mx6: Add initial support for the Hummingboard soloFabio Estevam
SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Disable VDDPU regulatorFabio Estevam
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-08-31i.MX6: Correct ANATOP_PFD (Phase Fractional Divider) register declarationsEric Nelson
Some _CLKGATE_MASK and _FRAC_MASK macros were wrong for PFD_480 and the PFD_528 macros were missing. Fortunately, the incorrect macros weren't being used. Since both the PFD_480 and PFD_528 registers have the same structure, and the fields are identical for [0..3] in bytes [0..3], so a single set of macros will suffice. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-08-31imx: add status reporting for HAB statusStefano Babic
Add functions to report the HAB (High Assurance Boot) status of e.g. i.MX6 CPUs. This is taken from git://git.freescale.com/imx/uboot-imx.git branch imx_v2009.08_3.0.35_4.0.0 cpu/arm_cortexa8/mx6/generic.c include/asm-arm/arch-mx6/mx6_secure.h Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-06-26imx6: fix GPR2 wrong definitionPierre Aubert
Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Dirk Behme <dirk.behme@gmail.com>
2013-04-28imx: Add useful fuse definitionsBenoît Thébaudeau
Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28imx: Homogenize and fix fuse register definitionsBenoît Thébaudeau
IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-22dma: Add i.MX6 support to drivers/dma/apbh_dma.cStefan Roese
This will be used by the i.MX6 NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22mx6: Add solo-lite variant supportFabio Estevam
mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-13spi: mxc_spi: Set master mode for all channelsFabio Estevam
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-02-12mx6: Disable Power Down Bit of watchdogFabio Estevam
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
2012-11-10mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky
Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-10-16mx6qsabreauto: Pass the board revision to the kernelFabio Estevam
The kernel from Freescale expects that the bootloader passes the board revision. Read the board revision and pass it via get_board_rev(). Without passing the board revision the kernel does not operate properly as the initialization of peripherals are different in revA versus revB boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfieldsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15i.MX6: Add ANATOP_PFD_480 bitfield constantsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15i.MX6: define IOMUX_GPR3 register bitfieldsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-09-01mxc: Define architecture identifierBenoît Thébaudeau
Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
2012-09-01MX: Set a common gpio.h for all i.MXStefano Babic
Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
2012-09-01imx-common/cmd_bmode.c: add imx bmode (bootmode) commandTroy Kisky
This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-10mx6: Allow mx6 to access the IPUv3 registersFabio Estevam
Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15i.MX6: add enable_sata_clock()Eric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-04-16imx: Remove unneeded/repititive definitions from imx headersVikram Narayanan
Remove gpio related unused/repititive definitions from imx headers. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-04-16i.MX6: define CACHELINE_SIZEEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2012-03-27mx6: Read silicon revision from registerFabio Estevam
Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
generated by cgit (git 2.34.1) at 2024-12-30 21:43:46 +0000