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By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Signed-off-by: Lei Wen <leiwen@marvell.com>
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For files like the drivers/serial/serial.c, it must include the platform
file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in
the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Add i2c support to dkb board with pantheon soc.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
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This patch adds the Multiple Function Pin configuration support for
Marvell PANTHEON SoCs
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
SoC versions Supported:
1) PANTHEON920 (TD)
2) PANTHEON910 (TTC)
Signed-off-by: Lei Wen <leiwen@marvell.com>
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