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This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning:
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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