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path: root/arch/arm/include/asm/mach-imx
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2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18arm: Don't include common.h in header filesSimon Glass
It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10cmd: nandbcb: Reconstruct the nandbcb tool for all platformsHan Xu
The original nandbcb tool was designed for imx6 only, when trying to leverage it to replace the kobs-ng tool, we found the design is not friendly for supporting all platforms. To support all iMX6/7/8 platforms and for easy further maintain, I reconstruct the structure of the tool. The main changes including: 1. Use platform_data to determine the logic branches rather than simply use SOC name. 2. More data structures as parameter for functions. 3. Global variables to define the FCB/DBBT/FW locations. 4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout. 5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB. 6. Dump and compare all written FCB/DBBT to verify data integrity. The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: nand: support GPMI NAND driver for i.MX8Peng Fan
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: mxs_nand: fix the gf_13/14 definition issueHan Xu
gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mxs_nand: Add support for i.MX8MYe Li
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: mxs: correct bitflip for erased NAND pagePeng Fan
This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/ commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10fec: Move imx_get_mac_from_fuse declare to imx fileYe Li
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp, we have two different ENET controllers and both need to call this function. So decouple its declare from fec driver. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10imx: add module fuse supportPeng Fan
There are different parts from one SoC. Take i.MX6ULL for example, some part might not have ENET, some might have; some might not have USB, some might have. The information could be got from OCOTP, to make one image support the different parts, we need runtime disable linux kernel dts node and uboot driver probe if the corresponding module not exists in the part. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: update is_imx6ull to include i.MX6ULZPeng Fan
Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could share same macro, then we no need to add is_imx6ulz in various drivers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: imx8m: add i.MX8MN variants supportPeng Fan
Add i.MX8MN variants support Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: imx8m: add i.MX8MQ Dual and QuadLite supportPeng Fan
Add i.MX8MQ Dual and QuadLite variants. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: fix cpu_type helperPeng Fan
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type, extend it to 0x1ff. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-04-18video: mxsfb: add support for i.MXRTGiulio Benetti
Add support for i.MXRT by adding CONFIG_IMXRT in register structure and adding .compatible = "fsl,imxrt-lcdif". Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-08imx: add i.MX8MP PE propertyPeng Fan
i.MX8MP does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: get cpu id/type of i.MX8MPPeng Fan
Support get i.MX8MP cpu id and cpu type Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-07mach-imx: bootaux: elf firmware supportIgor Opaniuk
Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). ELF64 binaries isn't supported yet. This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-12-06board: colibri_imx7: reserve DDR memory for Cortex-M4Igor Opaniuk
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Use the linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-05imx: add rom api supportPeng Fan
i.MX8MN support loading images with rom api, so we implement reuse board_return_to_bootrom to let ROM loading images. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx: add i.MX8MN PE propertyPeng Fan
i.MX8MN does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8mn: support get_cpu_revPeng Fan
Add a dummy cpu type and support get_cpu_rev for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx: nandbcb: add support for i.MX7Igor Opaniuk
Add support for updating FCB/DBBT on i.MX7: - additional new fields in FCB structure - Leverage hardware BCH/randomizer for writing FCB Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03imx: gpmi: add defines for hw randominizerIgor Opaniuk
Extend GPMI Integrated ECC Control Register Description, include additional defines for enabling randomizer function and providing proper randomizer type. For additional details check i.MX7 APR, section 9.6.6.3 GPMI Integrated ECC Control Register Description (GPMI_ECCCTRLn) Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03mach-imx: Adding new argument for SIP call interfaceYe Li
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so update the interface to add new argument. Signed-off-by: Ye Li <ye.li@nxp.com> [agust: fixed imx8m-power-domain build] Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03ARM: imx: Fix bmode detection from grp10Claudius Heine
imx6_is_bmode_from_gpr9 always returns false, because IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return. This moves the function body into imx6_src_get_boot_mode, since that is the only one using it and it is on the same abstraction level (accessing registers directly). Signed-off-by: Claudius Heine <ch@denx.de>
2019-10-14imx :hab: Add hab version commandSjoerd Simons
THe RVT data includes a major and minor version in its header parameter. Add a new command to print this out. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-10-08imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08imx: add i.MX8MM PE propertyPeng Fan
i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX8MM cpu typePeng Fan
Add i.MX8MM cpu type and related helper functions Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: sys_proto: add is_imx8qm helperPeng Fan
Add is_imx8qm helper which could be used by SoC and Driver code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX6ULZ cpu typePeng Fan
Add i.MX6ULZ cpu type and helper. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-09-02i2c: mxc: add CONFIG_CLK supportPeng Fan
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-07-19i.MX6: nand: add nandbcb command for imxShyam Saini
Writing/updating boot image in nand device is not straight forward in i.MX6 platform and it requires boot control block(BCB) to be configured. It becomes difficult to use uboot 'nand' command to write BCB since it requires platform specific attributes need to be taken care of. It is even difficult to use existing msx-nand.c driver by incorporating BCB attributes like mxs_dma_desc does because it requires change in mtd and nand command. So, cmd_nandbcb implemented in arch/arm/mach-imx BCB contains two data structures, Firmware Configuration Block(FCB) and Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area, page address of firmware. On summary, nandbcb update will - erase the entire partition - create BCB by creating 2 FCB/DBBT block followed by 1 FW block based on partition size and erasesize. - fill FCB/DBBT structures - write FW/SPL on FW1 - write FCB/DBBT in first 2 blocks for nand boot, up on reset bootrom look for FCB structure in first block's if FCB found the nand timings are loaded for further reads. once FCB read done, DTTB will load and finally firmware will be loaded which is boot image. Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage information. Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
2019-04-25imx: sip: add call_imx_sip_ret2Peng Fan
This function will be used by i.MX8 fuse driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-13video: ipuv3: add DM_VIDEO supportAnatolij Gustschin
Extend the driver to build with DM_VIDEO enabled. DTS files must additionally include 'u-boot,dm-pre-reloc' property in soc and ipu nodes to enable driver binding to ipu device. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-01-28ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognitionLukasz Majewski
According to "Table 5-1. Boot Device Select" (page 335, i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017) the BOOT_CFG1[3] have following values (regarding EIM booting): 0 - NOR flash and 1 - ONENAND This commit provides correct identification of the boot medium for IMX6Q boards booting from NOR memory (MCCMON6 is one of them). Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01imx: rename mx8m,MX8M to imx8m,IMX8MPeng Fan
Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01imx: introduce is_imx8mq helperPeng Fan
Introduce is_imx8mq header macro Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-10-22imx: add i.MX8 cpu typePeng Fan
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22imx: boot_mode: Add FLEXSPI boot entryPeng Fan
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-07-23arm, imx6: add alternative PAD_CTL_DSE constantsMark Jonas
Not all i.MX6 pads use the same drive strength table. So far only the 240 Ohm to 34 Ohm table was available. Because the constants used have speaking names it can be confusing to use e.g. PAD_CTL_DSE_48ohm when according to the reference manual 52 Ohm is the correct value. This patch adds the 260 Ohm to 37 Ohm table. For example, the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register (SD-card clock) uses the added table. Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-26arm,imx6: fix PAD_CTL_SPEED_LOW constantMark Jonas
For most i.MX6 processors the PAD_CTL_SPEED_LOW constant is the same. Only the i.MX6 SoloLite is an exemption. So far the code did not consider that. Additionally, for a few i.MX6 processors the code used the wrong value for the constant. This patch fixes the PAD_CTL_SPEED_LOW constant for: - i.MX6 Solo [1] - i.MX6 DualLite [1] - i.MX6 Dual [2] - i.MX6 Quad [2] - i.MX6 DualPlus [3] - i.MX6 QuadPlus [3] Before, it was already correct for: - i.MX6 SoloLite [4] - i.MX6 SoloX [5] - i.MX6 UtraLite [6] - i.MX6 ULL [7] [1] https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf [2] https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf [3] https://www.nxp.com/docs/en/reference-manual/iMX6DQPRM.pdf [4] https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf [5] https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf [6] https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf [7] https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-04-15imx: mx7: snvs: Add an SNVS init routineBryan O'Donoghue
Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-03-11imx: hab: Make usage of packed attribute consistentBryan O'Donoghue
commit cd2d46003ce1 ("arm: imx: hab: Add IVT header definitions") declares struct ivt_header as "__attribute__((packed))". commit ed286bc80e9d ("imx: hab: Check if CSF is valid before authenticating image") declares struct hab_hdr with __packed. This patch makes the __packed convention consistent. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-03-11imx: hab: Fix usage of packed attributeBryan O'Donoghue
commit ed286bc80e9d ("imx: hab: Check if CSF is valid before authenticating image") makes use of "__packed" as a prefix to the "struct hab_hdr" declaration. With my compiler "gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)" we get: ./arch/arm/include/asm/mach-imx/hab.h:42:25: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘{’ token struct __packed hab_hdr { Fix this problem by including <linux/compiler.h> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-22arm: imx: hab: Define HAB_RVT_BASE according to the processor versionBreno Lima
Currently the following devices are using a different definition for ROM Vector Table addresses: - i.MX6DQP = All rev - i.MX6DQ >= rev 1.5 - i.MX6SDL >= rev 1.2 There is no need to create a new RVT macros since the only update were the RVT base address. Remove HAB_RVT_*_NEW macros and define a new RVT base address. More details about RVT base address can be found on processors Reference Manual and in the following documents: EB803: i.MX 6Dual/6Quad Applications Processor Silicon Revision 1.2 to 1.3 Comparison EB804: i.MX 6Solo/6DualLite Application Processor Silicon Revision 1.1 to 1.2/1.3 Comparison Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-22imx: hab: Check if CSF contains deprecated commandsUtkarsh Gupta
Write, Check and Set MID commands have been deprecated from the Code Signing Tool (CST) v2.3.3 and will not be implemented in newer versions of HAB, hence the following features are no longer available: - Write Data - Clear Mask - Set Mask - Check All Clear - Check All Set - Check Any Clear - Check Any Set - Set MID The inappropriate use of Write Data command may lead to an incorrect authentication boot flow. Since no specific application has been identified that requires the use of any of these features, it is highly recommended to add this check. Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-22imx: hab: Check if CSF is valid before authenticating imageUtkarsh Gupta
For proper authentication the HAB code must check if the CSF is valid. Users must call the csf_is_valid() function to parse the CSF prior to authenticating any additional images. The function will return a failure if any of the following invalid conditions are met: - CSF pointer is NULL - CSF Header does not exist - CSF does not lie within the image bounds - CSF command length zero Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-04i2c: imx: Take mx6dqp in consideration in the I2C_PADS_INFO macroEran Matityahu
We should take the MX6DP and MX6QP options in consideration in the I2C_PADS_INFO macro. Based on a patch by Pierluigi Passaro <pierluigi.p@variscite.com> Signed-off-by: Eran Matityahu <eran.m@variscite.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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