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2017-06-08sunxi: Add selective DRAM type and timingIcenowy Zheng
DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08sunxi: Rename bus-width related macros in H3 DRAM codeIcenowy Zheng
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to identify whether the DRAM is half-width. As H3 itself come with 32-bit DRAM, the two modes of the bit used to be named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM they're really 8-bit and 16-bit. Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c. This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08sunxi: makes an invisible option for H3-like DRAM controllersIcenowy Zheng
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-05common: arm: freescale: layerscape: Move header files out of common.hSimon Glass
We should not have an arch-specific header file in common.h. Adjust the board files a little so it is not needed, and drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: freescale: Move arch-specific imx code to arch-imxSimon Glass
These declarations should not be in common.h. Move them to an arch-specific header. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05arm: Include asm/setup.h explictlySimon Glass
Include this header where needed so we do not need to rely on common.h. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05arm: Add declarations to avoid needing to include headersSimon Glass
At present common.h includes various ARM-specific headers. In preparation for dropping this, add a few explicit declarations. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05arm: Make u-boot-arm.h a private headerSimon Glass
Rather than including this arch-specific header file in common.h, include it from within arm's u-boot.h header. Also drop the comment about something to be fixed. It has been there forever and it is not clear what it means. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05samsung: Drop s3c24x0 arch-specific codeSimon Glass
This is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05t81xx: Migrate TI81XX/TI816X/TI814X symbols to KconfigTom Rini
The symbol CONFIG_TI81XX is used for the parts that are common to the TI816x and TI814x SoCs and are not part of CONFIG_ARCH_OMAP2PLUS nor CONFIG_AM33XX. It however has so few uses that we can just modify the code to check for both and drop the symbol. The symbols CONFIG_TI816X and CONFIG_TI814X are for the repective SoCs. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05ti816x: Rework DDR initialization sequenceTom Rini
The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01armv8: layerscape: Enabling loading PPA during SPL stageYork Sun
Loading PPA in SPL puts the rest of U-Boot (including RAM version loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded, PSCI is available. Signed-off-by: York Sun <york.sun@nxp.com>
2017-05-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23board: freescale: ls2080ardb: Enable SD interface for RevF boardPriyanka Jain
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-22Merge git://git.denx.de/u-boot-sunxiTom Rini
trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't get Kconfig errors on platforms without SPL, ie sandbox (without SPL). Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_CMD_HASH to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_HASH Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Rework slightly, enable on some boards again] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_CMD_ESBC_VALIDATE to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-22lib: move hash CONFIG options to KconfigTom Rini
Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_SPL_BOARD_INIT to KconfigLey Foon Tan
This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> [trini: Update the Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-18i.MX6UL: geam6ul: Add SETUP_IOMUX_PADSJagan Teki
Add generic SETUP_IOMUX_PADS function, for imx6ul mux pads. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-05-17sunxi: Store the device tree name in the SPL headerSiarhei Siamashka
This patch updates the mksunxiboot tool to optionally add the default device tree name string to the SPL header. This information can be used by the firmware upgrade tools to protect users from harming themselves by trying to upgrade to an incompatible bootloader. The primary use case here is a non-removable bootable media (such as NAND, eMMC or SPI flash), which already may have a properly working, but a little bit outdated bootloader installed. For example, the user may download or build a new U-Boot image for "Cubieboard", and then attemept to install it on a "Cubieboard2" hardware by mistake as a replacement for the already existing bootloader. If this happens, the flash programming tool can identify this problem and warn the user. The size of the SPL header is also increased from 64 bytes to 96 bytes to provide enough space for the device tree name string. [Andre: split patch to remove OF_LIST hash feature] Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2017-05-15Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2017-05-15sunxi: Add clock support for TV encoderJernej Skrabec
This patch adds support for TV encoder clocks which will be used later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
2017-05-15sunxi: video: Split out TVE codeJernej Skrabec
Newer SoCs use same TV encoder unit. Split it out so it can be reused with new DM video driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
2017-05-15Kconfig: USB: Migrate CONFIG_USB_EHCI to CONFIG_USB_EHCI_HCDTom Rini
In order to be able to migrate the various SoC EHCI CONFIG options we first need to finish the switch from CONFIG_USB_EHCI to CONFIG_USB_EHCI_HCD. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Marek Vasut <marex@denx.de>
2017-05-15omap5: Migrate CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC to KconfigTom Rini
While in theory this value could be used in places outside of "omap5" (such as OMAP4), we only make use of it today in OMAP5, so place the Kconfig entry there. Given that Kconfig lets us provide a default, we drop CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC entirely. The contents of doc/README.omap-reset-time make a good help entry, so adjust them slightly and delete the file. Move the comment about range to where we use the value now, and have Kconfig enforce the upper bound. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-15TI: Drop 'CONFIG_OMAP'Tom Rini
In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-15i2c: Drop use of CONFIG_I2C_HARDSimon Glass
This option is pretty old. It predates CONFIG_SYS_I2C which is itself deprecated in favour of driver model. Disable it for all boards. Also drop I2C options which depend on this. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-12arm: change tbu/l type to unsigned intPeng Fan
Change tbu/l type to unsigned int. >From the timer file for arm, "(((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;" is used, This piece code is based on tbu/tbl is 32bits, so change the type to unsigned int. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2017-05-12arm: am33xx: Add support for mulitiple PLL input frequenciesLokesh Vutla
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12arm: am33xx: Fix MPU opp selectionLokesh Vutla
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data: MPU values for PG 2.0 and later(Package ZCZ and ZCE): ------------------------------------------------------- | | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 | ------------------------------------------------------- There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages. [1] http://www.ti.com/lit/ds/symlink/am3356.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12configs: convert CONFIG_SYS_MPUCLK to KconfigLokesh Vutla
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-12armv7m: add MPU configuration supportVikas Manocha
Cortex-M archs support option memory protection unit (MPU). MPU is used to set the memory types, attributes, access permissions for different regions, cache policies of the device. e.g. using MPU it is possible to configure memory region as device memory or strongly ordered, memory attributes like execute never, cache policies like write-back or write-through. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-12armv7m: correct mpu region size define for 8MB sizeVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-11dm: mmc: omap_hsmmc: Update to support of-platdataLokesh Vutla
This is to aid platforms that uses OF_PLATDATA. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-11arm: Support cache invalidateSimon Glass
At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-10rockchip: rk3288: grf: Add grf define for mipi dsiEric Gao
Add grf register define for rk3288 mipi dsi Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: video: vop: Add mipi display mode for rk3399Eric Gao
Add mipi display mode for rk3399 vop, so that we can use mipi panel for display. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: video: Add mipi driver support for rockchip socEric Gao
Add basic driver for mipi display on rockchip soc platform. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: include: grf: Add GRF register declaration for mipi dsiEric Gao
Add GRF register declaration for mipi dsi. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10rockchip: pinctrl: rk3399: add support for the HDMI I2C pinsPhilipp Tomsich
To add HDMI support for the RK3399, this commit provides the needed pinctrl functionality to configure the HDMI I2C pins (used for reading the screen's EDID). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: reserve memory for rk3399 ATF dataKever Yang
There are 3 regions used by rk3399 ATF: - bl31 code, located at 0x10000; - cortex-m0 code and data, located at 0xff8c0000; - bl31 data, located at 0xff8c1000 ~ 0xff8c4000; SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will be memory corrupt after SPL loads the ATF image. More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add gmac io strength supportKever Yang
GMAC controller need to init the tx io driver strength to 13mA, just like the description in dts pinctrl node, or else the controller may only work in 100MHz Mode, and fail to work at 1000MHz mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add support for the SPI5 controllerPhilipp Tomsich
This commit adds support for the pin-configuration of the SPI5 controller of the RK3399 through the following changes: * grf_rk3399.h: adds definition for configuring the SPI5 pins in the GPIO2C group * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3 through SPI5 to the appropriate pin-config function; implements the pin-configuration for PERIPH_ID_SPI5 using the GPIO2C group X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-09omap_hsmmc: update struct hsmmc to accommodate omap3 from DTAdam Ford
This patch changes the way DM_MMC calculates offset to the base register of MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3. This patch will now add in the offset to the base address based on the .compatible flags. Signed-off-by: Adam Ford <aford173@gmail.com> V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table. V1: Change ifdef to ignore OMAP3 Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2017-05-08aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com
Refactor SCU header to use consistent Mask & Shift values. Now, consistently, to read value from SCU register, mask needs to be applied before shift. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-12-29 09:28:34 +0000