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2016-10-28Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
2016-10-26arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial supportJagan Teki
Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-24imx: mx7: Add plugin supportPeng Fan
Add mx7_plugin.S which calls boot rom setup function, generate the second ivt, and jump back to boot rom. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-24imx: mx6: Add plugin supportPeng Fan
Add mx6_plugin.S which calls boot rom setup function, generate the second ivt, and jump back to boot rom. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
2016-10-18arm: Add PSCI shutdown functionAlexander Graf
Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-18arm: Disable HVC PSCI calls by defaultAlexander Graf
All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-12Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
2016-10-08Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-10-08ARM: AM437X: Add Silicon ID supportLokesh Vutla
Add silicon ID code for AM437x silicon. This can be used to print the cpu info using CONFIG_DISPLAY_CPUINFO. Also printing "CPU :" along with cpu name in order to be consistent with other OMAP platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-08arm: Add return value argument to longjmpAlexander Graf
The normal longjmp command allows for a caller to pass the return value of the setjmp() invocation. This patch adds that semantic to the arm implementation of it and adjusts the efi_loader call respectively. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-08ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()Masahiro Yamada
The KeyStone platform has its own clk_get_rate() but its prototype is different from that of the common-clk (clk-uclass) framework. Prefix the KeyStone specific implementation with ks_ in order to avoid name-space conflict. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06ARM: Add register defines for am33xx ePWM registerstomas.melin@vaisala.com
Register definitions needed for configuring the ePWM module. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2016-10-06ARM: Introduce function to switch to hypervisor modeKeerthy
On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06ARM64: Add support for some of atomic64 operationsAdam Oleksy
These functions are needed in UBI/UBIFS on ZynqMP platform (ARM64). Signed-off-by: Adam Oleksy <adam.oleksy@nokia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2016-10-06Various, accumulated typos collected from around the tree.Robert P. J. Day
Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Stefan Roese <sr@denx.de>
2016-10-06spl: Move spl_board_load_image() into a generic headerSimon Glass
At present this is only used on ARM and sandbox, but it is just as applicable to other architectures. Move the function prototype into the generic SPL header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06armv7: ls1021a: Move DDR config options to KconfigYork Sun
Move DDR3, DDR4 and related config options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06armv8: fsl-layerscape: Move DDR config options to KconfigYork Sun
Move DDR3, DDR4 and realted options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to KconfigYork Sun
Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to KconfigYork Sun
Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06arm: Move SYS_FSL_IFC_BANK_COUNT to KconfigYork Sun
Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06arm: Move MAX_CPUS to KconfigYork Sun
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-06armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539Hou Zhiqiang
Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06armv8: fsl-layerscape: Fix "cpu status" commandYork Sun
The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
2016-10-06armv8: fsl-lsch2: enable snoopable sata read and writeTang Yuantian
By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06armv8: fsl-lsch2: adjust sata parameterTang Yuantian
The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-04imx-common: enlarge mux width to 4Peng Fan
For i.MX6, the mux width is 4, not 3. So enlarge the width. IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-10-04imx: iomux: fix snvs usage for i.MX6ULLPeng Fan
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
2016-10-04imx: imx6ull: adjust the ldo 1.2v bandgap voltagePeng Fan
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-10-04imx: mx6ull: Update memory map addressPeng Fan
Update memory map address for mx6ull. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-10-04imx: mx6ull: update clock settings and CCM register mapPeng Fan
Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-10-04imx-common: introduce is_mx6ullPeng Fan
Introduce is_mx6ull macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-10-04imx: mx6ull: add mx6ull major cpu typePeng Fan
Add i.MX6ULL major cpu type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-10-04imx: mx6ull: add iomux header filePeng Fan
Add iomux header file for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-10-03Merge git://git.denx.de/u-boot-rockchipTom Rini
2016-10-02arm: omap5: secure API for EMIF memory reservationsDaniel Allred
Create a few public APIs which rely on secure world ROM/HAL APIs for their implementation. These are intended to be used to reserve a portion of the EMIF memory and configure hardware firewalls around that region to prevent public code from manipulating or interfering with that memory. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-01rockchip: add boot-mode support for rk3288, rk3036Jacob Chen
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01rockchip: rkpwm: fix the register sequenceKever Yang
Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-10-01rockchip: rk3399: update PPLL and pmu_pclk frequencyKever Yang
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-09-30Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
2016-09-27dra7x: boot: add dfu bootmode supportB, Ravi
This patch enables the DFU boot mode support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-27ARM: tegra: add APIs the clock uclass driver will needStephen Warren
A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-27ARM: tegra: add peripheral clock init tableStephen Warren
Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-27mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2016-09-27mmc: tegra: priv struct and naming cleanupStephen Warren
struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-27mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren
pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDRYork Sun
Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-26Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun
Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2016-09-26armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun
Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>