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2018-01-10armv8: layerscape: sata: refine port register configurationYuantian Tang
Sata registers PP2C and PP3C are used to control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively. Calculate those parameters from port clock frequency. Overwrite those registers with calculated values to get better OOB timing. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driverPatrice Chotard
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers instead of board GPIO initialization. Remove stm32_gpio.c which is no more used and migrate structs stm32_gpio_regs and stm32_gpio_priv into arch-stm32f4/gpio.h to not break compilation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 clock driverPatrice Chotard
Use available DM clk_stm32f.c driver instead of dedicated mach-stm32/stm32f4/clock.c. Migrate periph_clock defines from stm32_periph.h directly in CLK driver. These periph_clock defines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK. Enable also CLK flag. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 serial driverPatrice Chotard
Remove serial_stm32.c driver and uart init from board file, use available DM serial_stm32x7.c driver compatible for STM32F4/F7 and H7 SoCs. The serial_stm32x7.c driver will be renamed later with a more generic name as it's shared with all STM32 Socs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10usb: rockchip: add the rockusb gadgetEddie Cai
this patch implement rockusb protocol on the device side. this is based on USB download gadget infrastructure. the rockusb function implements the rd, wl, rid commands. it can work with rkdeveloptool Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-09rockchip: clk: bind reset driverElaine Zhang
Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-08imx: initialize and use generic timer on i.MX 6UL/ULLStefan Agner
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM generic timer. This change makes use of the ARM generic timer in U-Boot. This is crucial to make the ARM generic timers usable in Linux since timer_init() initalizes the system counter module, which is necessary to use the generic timers CP15 registers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-04mx6ull: Handle the CONFIG_MX6ULL cases correctlyFabio Estevam
Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Breno Lima <breno.lima@nxp.com> Tested-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-01-03imx: spl: Fix NAND bootmode detectionEran Matityahu
commit 20f14714169 ("imx: spl: Update NAND bootmode detection bit") broke the NAND bootmode detection by checking if BOOT_CFG1[7:4] == 0x8 for NAND boot mode. This commit essentially reverts it, while using the IMX6_BMODE_* macros that were introduced since. Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not necessarily 0x0 in this case. Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf, like it was in the code before. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tim Harvey <tharvey@gateworks.com>
2017-12-29imx: Add a common way for detecting NXP boards revisionFabio Estevam
NXP development boards based on i.MX6/i.MX7 contain the board revision information stored in the fuses. Introduce a common function that can be shared by different boards and convert mx6sabreauto to use this new mechanism. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-12-18Merge git://git.denx.de/u-boot-rockchipTom Rini
2017-12-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-12-18rockchip: update boot0 hookKever Yang
Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not need it. The very beginning of U-Boot proper is different between armv7 and armv8: armv7 start with ARM_VECTORS while armv8 start with 'b reset'. Here is the map of very beginning for all cases: armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b reset' Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-14arm64: zynqmp: Add missing zynq_board_read_rom_ethaddr() prototypeMichal Simek
Add missing zynq_board_read_rom_ethaddr() prototype reported by sparse. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-12-13armv8: ls1043a/ls2080a: check SoC by device IDWenbin song
Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-12ARM: pxa: Remove unused ifdefsTuomas Tynkkynen
These ifdefs are protecting #include statements for files that have never existed. AFAICT this hardware.h has been copied from the kernel and the ifdefs have never served a role in U-Boot, so delete them. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-12ata: Migrate CONFIG_LIBATA to KconfigTuomas Tynkkynen
This symbol enables some library code used by various SATA drivers, so make this a non-user-visible symbol select'ed by the respective drivers, and let moveconfig handle the rest. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-12ata: Migrate CONFIG_SCSI_AHCI to KconfigTuomas Tynkkynen
And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-04Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-12-04armv8: mmu: fix page table mappingPeng Fan
To page mapping the lowest 2 bits needs to be 0x3. If not fix this, the final lowest 3 bits for page mapping is 0x1 which is marked as reserved. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-04ARM: arch-meson: build memory banks using reported memory from registersNeil Armstrong
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-Boot and Linux has the old address and size fixed. These SoCs have a register interface to get the two firmware reserved memory start and sizes. This patch adds a dynamic reservation of the memory zones in the device tree bootmem reserved memory zone used by the kernel in early boot. To be complete, the memory zones are also added to the EFI reserved zones. Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2]. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html Changes since v1: - switched the #if to if(IS_ENABLED()) to compile all code paths - renamed function to meson_board_add_reserved_memory() - added a mem.h header with comment - updated all boards ft_board_setup() Changes since RFC v2: - reduced preprocessor load - kept Odroid-C2 static memory mapping as exception Changes since RFC v1: - switch to fdt rsv mem table and efi reserve memory - replaced in_le32 by readl() Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [trini: Fix warning on khadas-vim over missing <asm/arch/mem.h> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-12-04ARM: arch-meson: add ethernet common init functionNeil Armstrong
Introduce a generic common Ethernet Hardware init function common to all Amlogic GX SoCs with support for the Internal PHY enable for GXL SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-04mtd: nand: Rename nand.h into rawnand.hMasahiro Yamada
This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-02rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASKPhilipp Tomsich
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15. Fix this to remove an "integer-overflow on shifted constant" warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-02rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASKPhilipp Tomsich
The PLL selector field for NANDC is only 2 bits wide. This fixes an 'int-overflow on shift' warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add pinctrl driverKever Yang
Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add clock driverKever Yang
Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-29stm32: migrate clock structs in include/stm32_rcc.hPatrice Chotard
In order to factorize code between STM32F4 and STM32F7 migrate all structs related to RCC clocks in include/stm32_rcc.h Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard
MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard
STM32F4 doesn't get rcc.h file, to avoid compilation issue, migrate RCC related defines from rcc.h to driver file and remove rcc.h file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: retrieve PWR base address from DTPatrice Chotard
PWR IP is used to enable over-drive feature in order to reach a higher frequency. Get its base address from DT instead of hard-coded value Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
2017-11-29bitops: collect BIT macros to include/linux/bitops.hMasahiro Yamada
Same macros are defined in various places. Collect them into include/linux/bitops.h like Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-28arm64: zynqmp: Add support for CG/EG/EV device detectionMichal Simek
Version string has unused fields 31:20 which can be used for exporting 9 bits from efuse IPDISABLE regs to recognize eg/cg/ev devices. These efuse bits are setup for certain devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU tableSiva Durga Prasad Paladugu
This patch provides a Kconfig option to use specified memory for MMU table using reserve_mmu platform specific routine. Here we used TCM space for MMU table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove slcr with mio status pin detectionMichal Simek
This code is not used on this platform and it is not called. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-27Merge git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27imx: Remove boolean parameter from wdog powerdown functionFabio Estevam
imx_set_wdog_powerdown() is always used to disable the power down enable bit, so remove the boolean parameter of the function. It is also a bit strange to write a boolean value into registers, so this new version makes explicit that we are writing 0. While at it, rename it to imx_wdog_disable_powerdown(). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-11-27mx6ull: Fix WDOG3 base addressFabio Estevam
i.MX6ULL has the same WDOG3 base address as i.MX6UL, so take this into account in the base address definition. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-11-26rockchip: pinctrl: rk3399: add support for I2C8Philipp Tomsich
The RK3399 has a total of 9 I2C controllers. To support these, the enum in periph.h is extended and the mapping from the IRQ numbers to the peripheral-ids is extended to ensure that pinctrl requests are passed through to the function configuring the I2C pins. For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using communication with the FAN53555 connected on I2C8. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-21rockchip: add support for enter to bootrom download modeAndy Yan
Rockchip bootrom will enter download mode if it returns from spl/tpl with a non-zero value and couldn't find a valid image in the backup partition. This patch provide a method to instruct the system to back to bootrom download mode by checking the BROM_DOWNLOAD_FLAG register. As the bootrom download function relys on some modules such as interrupts, so we need to back to bootrom as early as possbile before the tpl/spl code override the interrupt configurations. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: make boot_mode related codes reused across all platformsAndy Yan
setup_boot_mode function use the same logic but different mode register address across all the rockchip platforms, so it's better to make this function reused across all the platforms, and let the mode register address setting from the config file. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: sysreset: merge into one common driverKever Yang
Use a common driver for all Rockchip SOC instead of one for each SoC. Use driver_data for reg offset. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: back-to-bootrom: allow passing a cmd to the bootromPhilipp Tomsich
The BROM supports forcing it to enter download-mode, if an appropriate result/cmd-word is returned to it. There already is a series to support this in review, so this prepares the (newly C-version) of the back-to-bootrom code to accept a cmd to passed on to the BROM. All the existing call-sites are adjusted to match the changed function signature. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21rockchip: back-to-bootrom: replace assembly-implementation with C-codePhilipp Tomsich
The back-to-bootrom implementation for Rockchip has always relied on the stack-pointer being valid on entry, so there was little reason to have this as an assembly implementation. This provides a new C-only implementation of save_boot_params and back_to_bootrom (relying on setjmp/longjmp) and removes the older assembly-only implementation. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21arm: provide a PCS-compliant setjmp implementationPhilipp Tomsich
The previous setjmp-implementation (as a static inline function that contained an 'asm volatile' sequence) was extremely fragile: (some versions of) GCC optimised the set of registers. One critical example was the removal of 'r9' from the clobber list, if -ffixed-reg9 was supplied. To increase robustness and ensure PCS-compliant behaviour, the setjmp and longjmp implementation are now in assembly and closely match what one would expect to find in a libc implementation. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21arm: make save_boot_params_ret prototype visible for AArch64Philipp Tomsich
The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21rockchip: boot0 hook: support early return for RK3188/RK3066-style BROMPhilipp Tomsich
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data from NAND into SRAM and executes it. Then, following a return to bootrom, the BROM loads additional code to SRAM (not overwriting the first block read) and reenters at the same address as the first time. To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using this model of having to count entries, this commit adds code to the boot0 hook to track the number of entries and handle them accordingly. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21bcm281xx: boot0 hook: adjust to unified boot0 semanticsPhilipp Tomsich
This updates the BCM281xx boot0-hook to the updated boot0 semantics by emitting _start and the vector table before the boot0 hook (as was the case before). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21bcm235xx: boot0 hook: adjust to unified boot0 semanticsPhilipp Tomsich
This updates the BCM235xx boot0-hook to the updated boot0 semantics by emitting _start and the vector table before the boot0 hook (as was the case before). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Version-changes: 5 - ran 'whitespace-cleanup'
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