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2019-11-08fsl-layerscape: add missing SATA3 and SATA4 base addressesLaurentiu Tudor
LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-03imx: nandbcb: add support for i.MX7Igor Opaniuk
Add support for updating FCB/DBBT on i.MX7: - additional new fields in FCB structure - Leverage hardware BCH/randomizer for writing FCB Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03imx: gpmi: add defines for hw randominizerIgor Opaniuk
Extend GPMI Integrated ECC Control Register Description, include additional defines for enabling randomizer function and providing proper randomizer type. For additional details check i.MX7 APR, section 9.6.6.3 GPMI Integrated ECC Control Register Description (GPMI_ECCCTRLn) Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03mach-imx: Adding new argument for SIP call interfaceYe Li
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so update the interface to add new argument. Signed-off-by: Ye Li <ye.li@nxp.com> [agust: fixed imx8m-power-domain build] Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx: imx8mq: add init_nand_clkPeng Fan
Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF, so we still use legacy mode to configure the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03ARM: imx: Fix bmode detection from grp10Claudius Heine
imx6_is_bmode_from_gpr9 always returns false, because IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return. This moves the function body into imx6_src_get_boot_mode, since that is the only one using it and it is on the same abstraction level (accessing registers directly). Signed-off-by: Claudius Heine <ch@denx.de>
2019-11-03mx6: clock: Introduce disable_ipu_clock()Fabio Estevam
Introduce disable_ipu_clock(). This is done in preparation for configuring the NoC registers on i.MX6QP in SPL. Afer the NoC registers are set the IPU clocks can be disabled. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-25sunxi: set PIO voltage to hardware-detected value on startup on H6Icenowy Zheng
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25sunxi: H6: DRAM: Add support for half DQJernej Skrabec
Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Maxime Ripard <mripard@kernel.org>
2019-10-21armv8: Update LX2160A/LX2120A/LX2080A SVR valueWasim Khan
LX2160A/LX2120A/LX2080A SVR value should be 0x873600/0x873620/0x873602 Previous values were valid only if CAN fuse is blown. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21armv8: ls1028a: disable multimedia for ls1027a, ls1017aYuantian Tang
ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a. Both ls1027a and ls1017a personalities are lower functionality version which doesn't support the multimedia subsystems, like LCD, GPU. To disable multimedia feature on non-multimedia version, set the status property to disabled in dts nodes. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21armv8: fsl-layerscape: Make USB masters snoopableRan Wang
Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21armv7: ls102xa: Update SCFG_QSPI_CLKSEL valueKuldeep Singh
Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5 which means ClusterPLL/16 Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21armv8: ls1028a: Add more personalities supportYuantian Tang
Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-14Merge tag 'u-boot-imx-20191014' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191014 ------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628 - logicpd pinmux - i.MX7ULP: imx_ddr_size - fixes Toradex i.MX6/i.MX7 - pico-imx7d - tpc70 converted to DM - New Board: meerkat96 - add HAB version command - i.MX8 : imx8: Jump from alias to OCRAM address at SPL init imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-14Merge tag 'mmc-10-10-2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - Add sdhci driver for Broadcom iProc platform - Add a driver callback for power-cycle for mmc - Implement host_power_cycle callback for stm32_sdmmc2 - spl: dm_mmc: Initialize only the required mmc device
2019-10-14imx :hab: Add hab version commandSjoerd Simons
THe RVT data includes a major and minor version in its header parameter. Add a new command to print this out. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-10-13imx8: Jump from alias to OCRAM address at SPL initYe Li
When running SPL on iMX8, the A core starts at address 0 which is a alias to OCRAM 0x100000. The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB. But when using SPL DM, the size increase significantly and may exceed 96KB. So to fix the problem, we will change SPL linker address to OCRAM address 0x100000. And then jump to the absolute address not the PC relative address for entering OCRAM. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-11ARM: asm/io.h: remove redundant #if !defined(readb) blockRasmus Villemoes
readb is unconditionally defined earlier in io.h, so there's no point checking whether it's undefined. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-11ARM: asm/io.h: kill off confusing #ifdef __mem_pci blockRasmus Villemoes
No ARM board seems to define __mem_pci - and if it did, one would get tons of ./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined warnings, because readl and friends are unconditionally defined earlier in io.h. Moreover, the redefinitions lack the memory barriers that the first definitions have. So I'm guessing this is practically dead code. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-10drivers: mmc: Add sdhci driver for Broadcom iProc platformArun Parameswaran
Add SDHCI driver for iProc family of Broadcom devices. Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com> Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: Pavithra Ravi <pavithra.ravi@broadcom.com> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
2019-10-08imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08misc: imx8: add more scfw apiPeng Fan
Add more scfw api for clk/partition/seco usage The api will be used by ccf/partition/secure boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add clk support for i.MX8MMPeng Fan
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restructure clock.hPeng Fan
i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX8MM PE propertyPeng Fan
i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add pin header for i.MX8MMPeng Fan
Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: update imx-regs for i.MX8MMPeng Fan
i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and register layout change. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: imx-regs: drop unused register definitionsPeng Fan
Drop unused register definitions and structures for i.MX8MQ Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX8MM cpu typePeng Fan
Add i.MX8MM cpu type and related helper functions Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add support for i.MX8MQ power domain controllerPatrick Wildt
Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08imx: scu_api: add sc_pm_is_partition_startedPeng Fan
Add sc_pm_is_partition_started to check whether a partition has been started. This will be used to detect M4 partition booted up or not, then we could choose which dtb to use. If M4 is up, we need use dtb, such as imx8qm-mek-rpmsg.dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8: save args passed from ATFPeng Fan
We use information from ATF to know whether OP-TEE is running or not. So save args passed from ATF. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: scu_api: add sc_rm_set_master_sidPeng Fan
Add sc_rm_set_master_sid to set stream sid of masters to make sure they could use smmu. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: sys_proto: add is_imx8qm helperPeng Fan
Add is_imx8qm helper which could be used by SoC and Driver code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8: support parsing i.MX8 Container filePeng Fan
Add parsing i.MX8 Container file support, this is to let SPL could load images in a container file to destination address. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chipYe Li
The normal target frequency for ULP A7 core is 500Mhz, but now ROM set the core frequency to 413Mhz. So change it to 500Mhz in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08i.MX7ULP: Fix wrong i2c configuration nameYe Li
Wrong I2c driver configuration name is used in codes, so I2c driver is not built. Correct it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08i.MX7ULP: Fix PCC register bits mask and offset issueYe Li
The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08i.MX7ULP: Fix system reset after a7 rtc alarm expired.Bai Ping
The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access it. So check the CPU rev and not apply the settings for B0. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: i.MX7ULP: add get_boot_devicePeng Fan
Add get_boot_device for i.MX7ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Fabio Estevam <festevam@gmail.com>
2019-10-08imx: add i.MX6ULZ cpu typePeng Fan
Add i.MX6ULZ cpu type and helper. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-09-12fsl-layerscape: Add fsl_esdhc peripheral clock supportYinbo Zhu
Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-05mmc: Add Aspeed SD controller driverEddie James
Add support for the Aspeed SD host controller engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-05clk: aspeed: Add support for SD clockEddie James
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-02i2c: mxc: add CONFIG_CLK supportPeng Fan
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-08-25Convert CONFIG_ARCH_CPU_INIT to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_ARCH_CPU_INIT Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Felix Brack <fb@ltec.ch>
2019-08-23rockchip: rk3399: derive ethaddr from cpuidRohan Garg
Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. This is based off of Klaus Goger's work in 8adc9d Signed-off-by: Rohan Garg <rohan.garg@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-22armv8: ls1028a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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