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path: root/arch/arm/mach-meson/board-axg.c
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2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26ARM: meson: Add boot device discoveryNeil Armstrong
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol. When no other boot medium are available (or by forcing the USB mode), the ROM sets the primary USB port as device mode and waits for a Host to enumerate. When enumerated, a custom protocol described at [1] permits writing to memory and execute some specific FIP init code to run the loaded Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage. In this mode, we can load different binaries that can be used by U-boot like a script image file. This adds support for a custom USB boot stage only available when the boot mode is USB and the script file at a pre-defined address is valid. This support was heavily copied from the Sunxi Allwinner FEL U-Boot support. The tool pyamlboot described at [2], permits using this boot mode on boards exposing the first USB port, either as OTG or Host port. [1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md [2] https://github.com/superna9999/pyamlboot/blob/master/README.md Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: meson: Add support for AXG familyNeil Armstrong
This patch adds support for the Amlogic AXG SoC, which is very close from the Amlogic GXL SoCs with : - Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max - DDR Interface limited to DDR4 16bit - The whole physical register address space has been moved to 0xfxxxxxxx - The pinctrl setup has changed - The clock tree is different enough to use a different driver Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>