uboot-2021-rebase.git - uboot 2021 rebase, to fix booting on modern SD cards, from https://github.com/fifteenhex/u-boot/tree/am335x_som

Age	Commit message (Collapse)	Author
2017-11-30	rockchip: rk3036: sdram: correct setting for pll integer mode	Kever Yang
	According to rk3036 TRM, should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30	rockchip: rk3036: update clock driver for ddr	Kever Yang
	After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30	rockchip: rk3036: fix pll config for correct frequency	Kever Yang
	There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11	rockchip: rk3036: sync os_reg2 define with other soc	Kever Yang
	Rockchip using the same bit definition for dram info and write to os_reg, the col and bw info is not correct and let's fix it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2016-03-10	rockchip: rk3036: change ddr frequency to 400M	Lin Huang
	emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13	rockchip: rk3036 sdram setting cs1_row when rank larger than 1	huang lin
	only rank large than 1, we will use cs1_row, so check rank, when rank larger than 1, we set the cs1_row. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01	rockchip: add rk3036 sdram driver	huang lin
	add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>