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2017-11-21rockchip: make boot_mode related codes reused across all platformsAndy Yan
setup_boot_mode function use the same logic but different mode register address across all the rockchip platforms, so it's better to make this function reused across all the platforms, and let the mode register address setting from the config file. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: rk3188: move CONFIG_SPL_* entries from rk3188_common.h to KconfigPhilipp Tomsich
There still are a few CONFIG_SPL_* options selected using defines from rk3188_common.h instead of via Kconfig. This migrates those over to Kconfig. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: back-to-bootrom: allow passing a cmd to the bootromPhilipp Tomsich
The BROM supports forcing it to enter download-mode, if an appropriate result/cmd-word is returned to it. There already is a series to support this in review, so this prepares the (newly C-version) of the back-to-bootrom code to accept a cmd to passed on to the BROM. All the existing call-sites are adjusted to match the changed function signature. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21rockchip: rk3188: use boot0 hook to load up SPL in 2 stepsPhilipp Tomsich
For the RK3188, the BROM will attempt to load up the first stage image (SPL for the RK3188) in two steps: first 1KB to offset 0x800 in the SRAM and then the remainder to offset 0xc00 in the SRAM. It always enters at 0x804, though. With this changeset, the RK3188 boot removes the TPL (stub) stage and builds a single SPL binary that utilizes the early back-to-bootrom via the boot0-hook. Consequently, the passing of the saved boot params via pmu->os_reg[2] is also removed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: back-to-bootrom: replace assembly-implementation with C-codePhilipp Tomsich
The back-to-bootrom implementation for Rockchip has always relied on the stack-pointer being valid on entry, so there was little reason to have this as an assembly implementation. This provides a new C-only implementation of save_boot_params and back_to_bootrom (relying on setjmp/longjmp) and removes the older assembly-only implementation. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21rockchip: boot0 hook: support early return for RK3188/RK3066-style BROMPhilipp Tomsich
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data from NAND into SRAM and executes it. Then, following a return to bootrom, the BROM loads additional code to SRAM (not overwriting the first block read) and reenters at the same address as the first time. To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using this model of having to count entries, this commit adds code to the boot0 hook to track the number of entries and handle them accordingly. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21rockchip: enable boot0-hook for all Rockchip SoCsPhilipp Tomsich
Rockchip SoCs bootrom design is like this: - First 2KB or 4KB internal memory is for bootrom stack and heap; - Then the first 4-byte suppose to be a TAG like 'RK33'; - The the following memory address end with '0004' is the first instruction load and running by bootrom; Let's use the boot0 hook to reserve the first 4-byte tag for all the Rockchip SoCs. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Commit message taken from an older patch by:] Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-11-01rockchip: rk3328: fix rockchip_get_cru apiKever Yang
The API for get priv pointer is wrong, fix it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-01rk3288: spl: Add dram_init_banksizeJagan Teki
Falcon mode, is updating DDR dt node configuration through spl_fixup_fdt() so add appropriate DDR base and size through dram_init_banksize. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: spl: rk3399: implement chip-specific board_spl_was_booted_from()Philipp Tomsich
To support the new "same-as-spl" specifier in the boot-order on the RK3399, this implements the chip-specific mapping from the information obtainable from the BROM to a OF path name. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-orderPhilipp Tomsich
It is often desirable to configure the spl-boot-order (i.e. the order that SPL probes devices to find the FIT image containing a full U-Boot) such that it contains 'the same device the SPL stage was booted from' early on. To support this, we introduce the 'same-as-spl' specifier for the spl-boot-order property. This commit adds: - documentation for the new board_spl_was_booted_from() function that individual SoCs/boards should provide, if they can determine where the SPL was booted from - implements the new board_spl_was_booted_from() stub function - adds support for handling the 'same-as-spl' specifier and calling into the per-SoC/per-board support code. This also updates the documentation for the 'u-boot,spl-boot-order' property. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: spl: add documentation for spl_node_to_boot_device()Philipp Tomsich
In the expectation that the spl-boot-order code will eventually gain use outside of mach-rockchip: let's add documentation on the spl_node_to_boot_device() function, which is likely to become a publicly exported function. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: rk3399: make spl_board_init board-specificPhilipp Tomsich
The later-stage spl_board_init (as opposed to board_init_f) should set up board-specific details: these differ between the EVB-RK3399 and the RK3399-Q7 (Puma). This moves spl_board_init back into the individual boards and removes the unneeded functionality from Puma. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk322x: update the sysreg number for boot modeKever Yang
The boot mode for rk322x is stored in sysreg 0, update it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rk3288: vyasa: Add TPL supportJagan Teki
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288, it is not possible add new SPL features like Falcon mode or etc. So add TPL stage so-that adding new features to SPL is possible. - TPL: DRAM init, clocks - SPL: MMC, falcon, etc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01armv7: rk3288: Move configure_l2ctlr to commonJagan Teki
configure_l2ctlr will be shared between SPL and TPL so move them into asm/arch/sys_proto.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01armv7: Move L2CTLR read/write to commonJagan Teki
L2CTLR read/write functions are common to armv7 so, move them in to include/asm/armv7.h and use them where ever it need. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Backed out the change to arch/arm/mach-tegra/cache.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROMPhilipp Tomsich
Instead of directly calling into the back-to-bootrom code, the RK3399 common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a transfer back into the bootrom. With this factored out, the spl_board_init function can not be customised for each RK3399 board. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: rk3328: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3288: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3188: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3399: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: ram: rk3399: update reg map for of-platdataKever Yang
After Simon's patch, the dtoc can work with 64bit address, so we need to fix reg number for it. Depend on Simon's patch set: https://patchwork.ozlabs.org/cover/807266/ Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rk3288: Add Vyasa initial board supportJagan Teki
This patch adds support for Vyasa RK3288 initial board from Amarula Solutions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRFPhilipp Tomsich
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL enabled: this allows the use of syscon to retrieve the addresses of GRF and SGRF (except for the early debug UART setup, which runs so early that the device-model is not initialised). This removes the hard-coded addresses and goes through syscon to retrieve the base-addresses of GRF and SGRF. After that, we use the structure definitions to locate the respective registers. In addition to this, the inclusion of header files is also cleaned up: - all headers are included at the beginning (there was a spurious inclusion of the grf header from within a function) - all #include statements for unused headers are removed - the remaining #include statements are sorted (while keeping common.h included in front) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: rk322x: Disable integrated macphy for saving power consumingDavid Wu
Unfortunately, the integrated macphy default is enabled, which will increase power consuming, if we do not use this PHY. So let's disable it at first, which will save power consuming. If we really use it, then enable it in driver level. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: enable fastboot to set boot mode tagKever Yang
To support fastboot "fastboot reboot-bootloader" cmd. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08rockchip: rk3328: fix syscon id tableKever Yang
syscon id table need a dummy member as NULL ending, or else system will panic while try to match a compatible in this table as a list. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05rockchip: rk3288: Add reset reason detectionWadim Egorov
Sometimes it's helpful to know the reset reason caused in the SoC. Add reset reason detection for the RK3288 SoC. This will set an environment variable which represents the reset reason. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18rockchip: rk322x: update dram bank sizeKever Yang
The DRAM start address is not 0, so need to update the last bank size as: DRAM start addr + DRAM_SIZE - last bank start addr Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18rockchip: rk3399: spl: remove unused header inclusionPhilipp Tomsich
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the '#include'-statement. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-16env: Rename setenv() to env_set()Simon Glass
We are now using an env_ prefix for environment functions. Rename setenv() for consistency. Also add function comments in common.h. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk322x: set the DDR region as non-secure in SPLKever Yang
Disable the ddr secure region setting in SPL and the ddr memory becomes non-secure, every one can access it. the trust firmware like OPTEE should have the correct setting for it after SPL if there is one. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13rockchip: rk3368: spl: move SPL_LDSCRIPT to KconfigPhilipp Tomsich
With the new way of doing things (i.e. the hierarchical selection of SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting for the RK3368 from defconfig back into Kconfig. With this done, there should be no lingering cases of SPL_LDSCRIPT outside of Kconfig files. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3188: rock: adjust for SPL/TPL splitPhilipp Tomsich
With the changes to split SPL/TPL for the RK3368, I apparently missed some needed adjustments to the RK3188 Kconfig and rock_defconfig. This fixes build-issues for the rock board after applying the RK3368 enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT, TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols now. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: remove setup of secure timer from TPL/SPLPhilipp Tomsich
When using DM timers w/ the timer0 block within the RK3368, we no longer depend on the ARMv8 generic timer counting. This allows us to drop the secure timer initialisation from the TPL and SPL stages. The secure timer will later be set up by ATF, which starts the ARMv8 generic timer. Thus, there will be a dependency from Linux to the ATF through the ARMv8 generic timer... this seems reasonable, as Linux will require the ATF (and PSCI) to start up the secondary cores anyway (in other words: we don't add any new dependencies). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZEPhilipp Tomsich
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the whitelist (this time it's really happening!) and migrate the setting (only used on the RK3368-uQ7 so far) into Kconfig. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size ↵Philipp Tomsich
from SPL The RK3368 needs to have a different base-address and stack-pointer for its TPL stage. Now that we want to do this via Kconfig, we need to tick the appropriate 'TPL_NEEDS_...' boxes. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368Philipp Tomsich
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our header file. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13rockchip: board: lion-rk3368: add support for the RK3368-uQ7Philipp Tomsich
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm, MXM-230 edge connector compatible with the Qseven specification) form-factor system-on-module based on the octo-core Rockchip RK3368. It is designed, supported and manufactured by Theobroma Systems. It provides the following features: - 8x Cortex-A53 (in 2 clusters of 4 cores each) - (on-module) up to 4GB of DDR3 memory - (on-module) SPI-NOR flash - (on-module) eMMC - Gigabit Ethernet (with an on-module KSZ9031 PHY) - USB - HDMI - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368Philipp Tomsich
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as supported from Kconfig for the RK3368. As this is primarily tested on the RK3368-uQ7, we'll leave it to board's individual defconfig to enable. Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output during the early boot-up, as we turn on TPL and SPL. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: spl: add SPL supportPhilipp Tomsich
Adds SPL support for the RK3368 (assuming that our TPL stage has initialised DRAM and set up the memory firewall). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: spl: make spl-boot-order code reusable (split from rk3399)Philipp Tomsich
In order to reuse the support for the u-boot,spl-boot-order property from the rk3399, we split it into a reusable module that can be included by the SPL code for any of our boards. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: spl: add TPL supportPhilipp Tomsich
This adds the TPL support for the RK3368, including the u-boot-tpl.lds. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: add DRAM controller driver with DRAM initialisationPhilipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: Makefile: streamline SPL/TPL configurationPhilipp Tomsich
Handling TPL and SPL in the Makefile for mach-rockchip was based on nested if checks and/or if-else-if paths. This can be simplified and made more readable by using $(SPL_TPL_) and by introducing intermediate variables for the aggregation of SPL and TPL features. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: syscon: SGRF support for OF_PLATDATAPhilipp Tomsich
In TPL we will need to configure security in the SGRF of the RK3368. This change adds support for the SGRF as a syscon device, so we can retrieve its address range through the syscon API in TPL (and can avoid having to hard-code the address). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATAPhilipp Tomsich
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the added challenge of booting in AArch64, which increases the code size for TPL (particularily when using the LP64 programming model). For this reason we expect the RK3368 to always use OF_PLATDATA for its TPL stage. This change adds support for the MSCH, PMUGRF and GRF register regions in syscon, which are necessary for initialising the RK3368's DRAM controller. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: improve Kconfig text for the RK3368Philipp Tomsich
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste) and had a few typos and unnecessarily used UTF-8 characters. While fixing this, I also reformatted and further clarified the text (e.g. made the grouping into a a big and little cluster of 4 cores each explicit). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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