Age | Commit message (Collapse) | Author | |
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2017-05-18 | arm: socfpga: Restructure clock manager driver | Ley Foon Tan | |
Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> |