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2019-02-18arm: socfpga: gen5: remove hacked ETH RST handlingSimon Goldschmidt
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon. This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-01spl: Kconfig: Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPL_FS_EXT4Tien Fong Chee
Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPLY_FS_EXT4 so both obj-$(CONFIG_$(SPL_)FS_EXT4) and CONFIG_IS_ENABLED(FS_EXT4) can be used to control the build in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-01spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FATTien Fong Chee
Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT so obj-$(CONFIG_$(SPL_)FS_FAT) can be used to control the build in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-20arm: socfpga: stratix10: Enable Stratix10 FPGA ReconfigurationAng, Chee Hong
Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device tableAng, Chee Hong
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20arm: socfpga: stratix10: Add macros for mailbox's argumentsAng, Chee Hong
Add macros for specifying number of arguments in mailbox command. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10Ang, Chee Hong
Add a generic mailbox API for FPGA reconfig status which can be called by others. This new function accepts 2 different mailbox commands: CONFIG_STATUS or RECONFIG_STATUS. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-11-29arm: socfpga: fix SPL booting from fpga OnChip RAMSimon Goldschmidt
This patch prevents disabling the FPGA bridges when SPL or U-Boot is executed from FPGA onchip RAM. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29arm: socfpga: make config structs constSimon Goldschmidt
There are two config structs left in wrap_sdram_config.c that can be made const. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-03arm: socfpga: stratix10: add sgmii in phymode setupOoi, Joyce
Additional sgmii phymode is added in socfpga_phymode_setup() along with a minor fix for maximum number of GMACs. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
2018-10-03arm: socfpga: Remove unused function socfpga_emac_manage_reset()Ley Foon Tan
Remove code from the reset manager that is never called. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-09-15socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen
Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2018-08-24ARM: socfpga: Convert Arria10 to timer frameworkMarek Vasut
Switch the Arria10 from ad-hoc hardcoded timer to timer framework and the DW APB timer driver. This allows the A10 to extract timer information, like timer rate, from clock framework and thus DT instead of having it hardcoded in U-Boot configuration files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24ARM: socfpga: Reorder Arria10 SPLMarek Vasut
The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24arm: socfpga: stratix10: Fix mailbox urgent command with urgent registerLey Foon Tan
According to mailbox spec, software should send urgent command with urgent register instead of COUT location. This patch write urgent command index to urgent register. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoffLey Foon Tan
Code checking and setting EMAC use fpga is in populate_sysmgr_fpgaintf_module(). So, call to sysmgr_pinmux_init() instead of populate_sysmgr_pinmux(). In sysmgr_pinmux_init(), it will call to both populate_sysmgr_pinmux() and populate_sysmgr_fpgaintf_module(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-15arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Convert to clock frameworkMarek Vasut
Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut
The variables removed in this patch are never used, they are only ever assigned and then waste precious memory. Drop both the assignment and the variables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut
The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut
Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut
Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Zap unused reset codeMarek Vasut
Remove code from the reset manager that is never called. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Zap all the UART handling complexityMarek Vasut
The UART reset handling is now done via reset framework using the SoCFPGA reset driver. The UART console assignment is done using the DM and console framework. Nuke all this comlexity, since it is just duplicating the same functionality, badly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13ARM: socfpga: Enable DM I2C framework on A10Marek Vasut
Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Enable DM reset framework on A10Marek Vasut
Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Register the FPGA on A10 in SPL againMarek Vasut
The restructuring of the SPL dropped registration of the FPGA in SPL, readd it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Fixes: c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
2018-08-13arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt
Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: cyclone5: handle debug uartSimon Goldschmidt
If CONFIG_DEBUG_UART is enabled, correctly initialize the debug uart before console is initialized to debug early boot problems in SPL. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: spl_gen5: clean up malloc_base assignmentSimon Goldschmidt
In spl_gen5's board_init_f(), gd->malloc_base is manually assigned at the end of the function to point to sdram. This code is outdated as by now, the heap is switched to sdram by the common function spl_relocate_stack_gd() if the appropriate defines are set. As it was, the value assigned manually was directly overwritten by this common code, so remove the manual assignment. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: fix SPL on gen5 after moving to DM serialSimon Goldschmidt
There were NULL pointers dereferenced because DM was used too early without correct initialization: - malloc_simple returned NULL when called from preloader_console_init() because gd->malloc_limit was 0 - uclass_add dereferenced gd->uclass_root members which were NULL because dm_init (or one of its relatives) has not been called. All this is fixed by calling spl_early_init before calling preloader_console_init. This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek
Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-25ARM: socfpga: Init missing security policies on A10Marek Vasut
The Arria10 requires proper configuration of the NOC firewall, otherwise the access to certain areas of the LWHPS bridge fails in Linux. Add the missing setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25ARM: socfpga: Assure correct CPACR configurationMarek Vasut
Make sure the ARM CPACR register is zeroed out, this is mandatory on Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-19lib: fdtdec: Rename routine fdtdec_setup_memory_size()Siva Durga Prasad Paladugu
This patch renames the routine fdtdec_setup_memory_size() to fdtdec_setup_mem_size_base() as it now fills the mem base as well along with size. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-13Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-12arm: socfpga: Fixes: include <debug_uart.h>Ley Foon Tan
Fix compilation warning when enable CONFIG_DEBUG_UART. arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’: arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration] debug_uart_init(); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit onlyLey Foon Tan
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12ARM: socfpga: Assure correct ACTLR configurationMarek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ARM: socfpga: Pull DRAM size from DTMarek Vasut
Pull the DRAM size from DT instead of hardcoding it into U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan
Add do_bridge_reset() function for Arria 10, it is required by misc.c. arch/arm/mach-socfpga/built-in.o: In function `do_bridge': arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' make[1]: *** [u-boot] Error 1 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan
Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan
Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan
Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Restructure the SPL fileLey Foon Tan
Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan
Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan
Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan
Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan
Move bridge command to misc common driver, in preparation to used by other platforms. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit (git 2.34.1) at 2024-12-30 22:23:00 +0000