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2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-26ARM: uniphier: remove SPL support for ARMv8 SoCsMasahiro Yamada
It has been a while since ARM Trusted Firmware supported UniPhier SoC family. U-Boot SPL was intended as a temporary loader that runs in secure world. It is a maintenance headache to support two different boot mechanisms. Secure firmware is realm of ARM Trusted Firmware and now U-Boot only serves as a non-secure boot loader for UniPhier ARMv8 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-25ARM: uniphier: fix various sparse warningsMasahiro Yamada
Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-17ARM: uniphier: add weird workaround code for LD20Masahiro Yamada
When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot) This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20 SoC (Cortex-A72) hangs in U-Boot. The solution I found is to read sctlr_el1 and write back the value as-is. This should be no effect, but surprisingly fixes the problem for LD20 to boot. I do not know why. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-22ARM: uniphier: make SPL optional for ARVv8 SoCsMasahiro Yamada
We may want to run different firmware before running U-Boot. For example, ARM Trusted Firmware runs before U-Boot, making U-Boot a non-secure world boot loader. In this case, the SoC might be initialized there, which enables us to skip SPL entirely. This commit removes "select SPL" to make it configurable. This also enables the Multi SoC support for the UniPhier ARMv8 SoCs. (CONFIG_ARCH_UNIPHIER_V8_MULTI) Thanks to the driver model and Device Tree, the U-Boot proper part is now written in a generic way. The board/SoC parameters reside in DT. The Multi SoC support increases the memory footprint a bit, but the U-Boot proper does not have strict memory constraint. This will mitigate the per-SoC (sometimes per-board) defconfig burden. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-24ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada
This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-15armv8: mmu: Add support of non-identical mappingYork Sun
Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-09ARM: uniphier: insert dsb barrier to ensure visibility of storeMasahiro Yamada
I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24ARM: uniphier: add PH1-LD20 SoC supportMasahiro Yamada
This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>