Age | Commit message (Collapse) | Author |
|
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
For Electro-Magnetic Compatibility test.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|