Age | Commit message (Collapse) | Author |
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It turned out that DDR channel 2 was not working on ProXstream2
Vodka board. Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The umc-proxstream2.c defiens the same macros as in umc-regs.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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As mentioned in the log of commit 019df879a93e2 (ARM: uniphier: add
ProXstream2 and PH1-LD6b support), the DRAM init code was missing
for a long time. Finally, here it is. SPL works now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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