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2017-03-16rockchip: rk3288: sdram: use constants in ddrconf tableHeiko Stübner
Use defines to describe the bit shifts used to create the table for ddrconf register values. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-16rockchip: arm64: rk3399: syscon addition for rk3399Kever Yang
rk3399 has different syscon registers which may used in spl, add to support rk3399 spl. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16rockchip: clk: rk3399: update driver for splKever Yang
Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.hKever Yang
rk3399 grf register bit defenitions should locate in header file, so that not only pinctrl can use it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16rockchip: rk3288: use spl_early_init() instead of spl_init()Eddie Cai
Use spl_early_init() to make sure that early malloc() is initialised. This fixes booting on firefly-rk3288, for example. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
2017-03-16Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2017.05 - Move to DM clk driver - Add clk support for zynq_sdhci
2017-03-16Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-03-14board: Add STMicroelectronics STiH410-B2260 supportPatrice Chotard
This is a 96Board compliant board based on STiH410 SoC: - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU with PCB soldered antenna - Ethernet 1000-BaseT - SATA - HDMI - 2 x USB2.0 type A - 1 x USB2.0 type micro-AB - SD card slot - High speed connector (SD/I2C/USB interfaces) - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14STiH410-B2260: Add device treePatrice Chotard
This device tree has been extracted from v4.9 kernel Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14STiH410: Add STi SDHCI driverPatrice Chotard
Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-03-14gpio: do not include <asm/arch/gpio.h> for ARCH_STIPatrice Chotard
As no gpio.h is defined in arch/arm/include/asm/arch-stih410, to avoid compilation failure, do not include asm/arch/gpio.h. This is needed for example when including sdhci.h, which include asm/gpio.h>. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14STiH410: Add STi serial driverPatrice Chotard
This patch adds support to ASC (asynchronous serial controller) driver, which is basically a standard serial driver. This IP is common across other STMicroelectronics SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14arm: Add support for STMicroelectronics STiH410 socPatrice Chotard
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU part of the STiH407 family. It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-14armv7m: Add SysTick timer driverPhil Edworthy
The SysTick is a 24-bit down counter that is found on all ARM Cortex M3, M4, M7 devices and is always located at a fixed address. The number of reference clock ticks that correspond to 10ms is normally defined in the SysTick Calibration register's TENMS field. However, on some devices this is wrong, so this driver allows the clock rate to be defined using CONFIG_SYS_HZ_CLOCK. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-03-14arm: omap3: Bring back ARM errata workaround 725233Siarhei Siamashka
The workaround for ARM errata 725233 had been lost since commit 45bf05854bc94e (armv7: adapt omap3 to the new cache maintenance framework). Bring it back in order to avoid very difficult to reproduce, but actually encountered in the wild CPU deadlocks when running software rendered X11 desktop on OMAP3530 hardware. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Migrate to Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-14arm: omap3: Compile clock.c with -marm option to unbreak OMAP3530Siarhei Siamashka
Boards with OMAP3530 SoC fail to boot since commit bd2c4522c26d5 ("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)") because it enabled the use of Thumb2 for the SPL. Experiments have shown that the deadlock happens in the prcm_init() function from 'arch/arm/mach-omap2/omap3/clock.c'. This patch enforces the compilation of clock.c source file in ARM mode and makes the deadlock disappear. We are yet to figure out the root cause of the problem. Still this is somewhat better than having non-bootable boards for years. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-14LS1021ATWR: Modify u-boot size for sd secure bootVinitha Pillai
Raw uboot image is used in place of FIT image in secure boot. The maximum allocated size of raw u-boot bin is 1MB in memory map. Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB. The bootscript (BS_ADDR) and its header (BS_HDR_ADDR) offset on MMC have also been modified to accommodate the increase in uboot size. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: fsl-lsch3: Update VID supportPriyanka Jain
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like LS2088A, LS2080A differs from existing logic. -VDD voltage array is different -Registers are different -VDD calculation logic is different Add new function adjust_vdd() for LSCH3 compliant SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: fsl-layerscape: Updates DCFG register mapPriyanka Jain
Based on latest hardware documentation, update ccsr_gur structure (represents DCFG register map) Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: fsl-lsch2: add workaround for erratum A-010635Tang Yuantian
Read DMA operations causes CRC error on armv8 chassis 2 platforms due to the erratum A-010635. In order to support sata on these platforms, ECC needs to be disabled. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Update early MMU for DDR after initializationYork Sun
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: mmu: Add a function to change mapping attributesYork Sun
Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: ls2080a: Drop early MMU for SPL buildYork Sun
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Fix the sequence of changing MMU tableYork Sun
This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Update MMU mapping with actual DDR sizeYork Sun
Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Rewrite memory reservationYork Sun
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to KconfigYork Sun
Use Kconfig option instead of config macro in header file. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: ls2080a: Move CONFIG_FSL_MC_ENET to KconfigYork Sun
Use Kconfig option instead of config macro in header file. Clean up existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: Add global variable resv_ramYork Sun
Use gd->arch.resv_ram to track reserved memory allocation. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14ARM: dts: uniphier: more re-sync DT with LinuxMasahiro Yamada
For better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-14ARM: dts: uniphier: fix no unit name warningsMasahiro Yamada
Fix warnings reported when built with W=1, by DTC 1.4.2 or later: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-14ARM: dts: uniphier: remove skeleton.dtsi inclusionMasahiro Yamada
Linux Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated") declared that skeleton.dtsi was deprecated. Move the memory node below to suppress warnings of FDTGREP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-14ARM: uniphier: set DRAM_SPARSE flag for LD21 boardsMasahiro Yamada
Commit 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board parameters") accidentally unset the DRAM_SPARSE flag, and changed the physical map of the DRAM channels. Revive the original behavior. Fixes: 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board parameters") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Shunji Sato <sato.shunji@socionext.com>
2017-03-11arm: omap-common: Fix typo in CONFIG_OMAP54XX guardMatthijs van Duin
Some initialization was unintentionally being skipped on omap5. Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX") Signed-off-by: Matthijs van Duin <matthijsvanduin@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-11arm: OMAP2+: nandecc: propagate error to command return statusLadislav Michl
Currently nandecc returns zero even if underlaying omap_nand_switch_ecc function fails. Fix that by propagating error returned to command return value. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-03-09ARM: Migrate errata to KconfigTom Rini
This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09omap4: Migrate to using implyTom Rini
Move the default y options under arch/arm/mach-omap2/omap4/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09omap3: Migrate to using implyTom Rini
Move the default y options under arch/arm/mach-omap2/omap3/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09TI: Migrate board/ti/common/Kconfig to implyTom Rini
The option that we had set in board/ti/common/Kconfig as default y are best done with imply under the appropriate main Kconfig option instead. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09am335x_evm: Switch to using imply keywordTom Rini
These particular SPL options are part of what the ROM provides, but for compatibility with how we have previously used them, move them to being implied by the board being selected. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09do_smhload: fix return codeRyan Harkin
do_smhload was using a ulong to store the return value from smh_load_file. That returns an int, where -1 indicates an error. As a ulong will never be negative, smh_load_file errors were not detected and so_smhload always returned zero. Also, when errors were spotted, do_smhload was returning 1, rather than the enumeration CMD_RET_FAILURE (which is also 1). Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-03-09Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini
In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-01armv8: spl: Call spl_relocate_stack_gd for ARMv8Philipp Tomsich
As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-01armv5te: make 'ret lr' produce iinterworking 'bx lr'Albert ARIBAUD
Current ARM assembler helper for the 'return to caller' pseudo-instruction turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain in its current ARM state even when the routine doing the 'ret' was called from Thumb-1 state, triggering an undefined instruction exception. This causes early run-time failures in all boards compiled using the Thumb-1 instruction set (for instance the Open-RD family). ARMv5TE supports 'bx lr' which properly implements interworking and thus correctly returns to Thumb-1 state from ARM state. This change makes 'ret lr' turn into 'bx lr' for ARMv5TE. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2017-02-27arm: mach-omap2: Flush cache after FIT post-processing imageAndrew F. Davis
After we authenticate/decrypt an image we need to flush the caches as they may still contain bits of the encrypted image. This will cause failures if we attempt to jump to this image. Reported-by: Yogesh Siraswar<yogeshs@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-23ARM: uniphier: set up charge pump current for MPLL of LD11 SoCMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23ARM: uniphier: add simple eMMC load APIs instead of ROM APIMasahiro Yamada
Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20Masahiro Yamada
For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoCKotaro Hayashi
If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23ARM: uniphier: remove dram_nr_ch from board parametersMasahiro Yamada
This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit (git 2.34.1) at 2025-01-05 04:21:28 +0000