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2017-06-01fdt: Rename a few functions in fdt_supportSimon Glass
These two functions have an of_ prefix which conflicts with naming used in of_addr. Rename them: fdt_read_number fdt_support_bus_default_count_cells Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: core: Replace of_offset with accessor (part 2)Simon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Fix up inclusion of common.hSimon Glass
It is good practice to include common.h as the first header. This ensures that required features like the DECLARE_GLOBAL_DATA_PTR macro, configuration options and common types are available. Fix up some files which currently don't do this. This is necessary because driver model will soon start using global data and configuration in the dm/read.h header file, included via dm.h. The gd->fdt_blob value will be used to access the device tree and CONFIG options will be used to determine whether to support inline functions in the header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Use dm.h header when driver mode is usedSimon Glass
This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-31Merge git://www.denx.de/git/u-boot-marvellTom Rini
Mostly including the Armada 37xx pinctrl / gpio driver.
2017-05-31Kconfig: Finish migration of hashing commandsDaniel Thompson
Currently these (board agnostic) commands cannot be selected using menuconfig and friends. Fix this the obvious way. As part of this, don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v' and "we have a hashing command" as this makes the Kconfig logic odd. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> [trini: Re-apply, add imply for a few cases, run moveconfig.py, also migrate CRC32_VERIFY] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-31arm64: mvebu: Replace board specific with generic memory bank decodingStefan Roese
The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nathan Rossi <nathan@nathanrossi.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-05-31arm64: mvebu: armada-7040-db: Enable 10GB port 0 / SFI (KR)Stefan Roese
This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting the correct PHY type (KR / SFI) for the COMPHY driver and enabling the ethernet0 device node in the dts. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
2017-05-31arm64: mvebu: armada37xx: add pinctrl definitionGregory CLEMENT
Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
2017-05-31arm64: mvebu: Add pinctrl nodes for Armada 3700Gregory CLEMENT
Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Minor changes for U-Boot because of the slightly different dts version done by Stefan Roese. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
2017-05-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-05-23Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini
2017-05-23armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-bootSantan Kumar
This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043AAlison Wang
This patch is to adjust the memory mapping for FLash/SD card on LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN firmware load address, QE firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add LS2081ARDB board supportPriyanka Jain
LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23board: freescale: ls2080ardb: Enable SD interface for RevF boardPriyanka Jain
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-22Merge git://git.denx.de/u-boot-sunxiTom Rini
trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't get Kconfig errors on platforms without SPL, ie sandbox (without SPL). Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Kconfig: Add a CONFIG_IDE optionSimon Glass
At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate CONFIG_IDE option so that IDE support can be enabled without requiring the 'ide' command. Update existing users and move the ide driver into drivers/block since it should not be in common/. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-22Convert CONFIG_CMD_HDMIDETECT to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_HDMIDETECT Note that we cannot do 'default y if VIDEO' because this option is only enabled for a small subset of mx6 boards. Also this command is is not a great implementation (it doesn't use driver model). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_CMD_HASH to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_HASH Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Rework slightly, enable on some boards again] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_CMD_FUSE to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_FUSE Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-22Convert CONFIG_CMD_ESBC_VALIDATE to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_CMD_ENTERRCM to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_ENTERRCM Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-22lib: move hash CONFIG options to KconfigTom Rini
Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22Convert CONFIG_SPL_BOARD_INIT to KconfigLey Foon Tan
This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> [trini: Update the Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22ARM: rmobile: Move address of IICDVFS(I2C) to rcar-gen3-base.hNobuhiro Iwamatsu
The IICDVFS(I2C) set in r8a7796.h is common in rcar-gen3. This moves CONFIG_SYS_I2C_SH_BASE0 in rcar-gen3-base.h. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Allow R8A7796 Salvator-X configurationMarek Vasut
The Salvator-X can have both H3 and M3 CPU on it, drop the select R8A7795 to allow both configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Add R8A7796 supportMarek Vasut
Add Kconfig entry for the R8A7796 RCar M3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Handle R8A7796 r1.1 in the PRR codeMarek Vasut
The R8A7796 r1.1 reports itself as r2.0 , add quirk into the PRR code to fix this report. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Add R8A7796 into the CPU tableMarek Vasut
Add entry for the R8A7796 RCar M3 SoC into the CPU info table. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Add R8A7795 into the CPU tableMarek Vasut
Add entry for the R8A7795 RCar H3 SoC into the CPU info table. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Make the Gen3 SoC configurableMarek Vasut
Allow selecting the Gen3 SoC in preparation for RCar M3 . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Zap RCAR_GEN3_EXTRAM_BOOTMarek Vasut
This Kconfig option is not used on any board, so drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Import R8A7796 PFC and GPIO tablesMarek Vasut
Import the R8A7796 PFC and GPIO tables from the latest 3.5.3 release from Renesas . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-22ARM: rmobile: Update R8A7795 PFC and GPIO tablesMarek Vasut
Sync the PFC and GPIO tables with the latest 3.5.3 release from Renesas . This adds ES2.0 support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-05-18Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2017-05-18Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2017-05-18ARM: dts: am335x-evm: disable mmc3Jean-Jacques Hiblot
SDIO is not supported in u-boot, there is no point in enabling mmc3. For this purpose, add u-boot specific dtsi that this will be included automatically while building the dtb. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-18arm: socfpga: Enable build for Arria 10Ley Foon Tan
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add SPL support for Arria 10Ley Foon Tan
Add SPL support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: dts: Add dts and dtsi for Arria 10Ley Foon Tan
Device tree files for Arria 10 Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add misc support for Arria 10Ley Foon Tan
Add misc support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add pinmux for Arria 10Ley Foon Tan
Add pinmux support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add sdram header file for Arria 10Ley Foon Tan
Add sdram header file for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add system manager for Arria 10Ley Foon Tan
Add system manager register struct and macros for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add clock driver for Arria 10Ley Foon Tan
Add clock driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18arm: socfpga: Add reset driver support for Arria 10Ley Foon Tan
Add reset driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit (git 2.34.1) at 2025-01-06 15:06:22 +0000