summaryrefslogtreecommitdiff
path: root/arch/arm
AgeCommit message (Collapse)Author
2019-10-11arm: dts: k3-j721e-main: Add C66x DSP nodesLokesh Vutla
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add MAIN domain R5F cluster nodesLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5 cores are each added as child nodes to the corresponding main cluster node. Configure SS0 in split mode an SS1 in lockstep mode, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-mcu: Add MCU domain R5F cluster nodeLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11armv7R: dts: k3: am654: Add MCU_UART0 related definitionsAndreas Dannenberg
Although we currently use the MAIN_UART0 for R5 SPL console output there are cases where we require access to the MCU_UART0 as well for example in case of UART-based Y-Modem boot. To support these scenarios add related DTS definitions to be able to use that UART early on. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-11arm: K3: sysfw-loader: Allow loading SYSFW via Y-ModemAndreas Dannenberg
In order to allow booting TI K3 family SoCs via Y-Modem add support for loading System Firmware by tapping into the associated SPL core loader function. In this context also make sure a console is available and if not go ahead and activate the early console feature which allows bringing up an alternate full console before the main console is activated. Such an alternate console is typically setup in a way that the associated UART can be fully initialized prior to SYSFW services being available. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-11arm: K3: common: Allow for early console functionalityAndreas Dannenberg
Implement an early console functionality in SPL that can be used before the main console is being brought up. This helps in situations where the main console is dependent on System Firmware (SYSFW) being up and running, which is usually not the case during the very early stages of boot. Using this early console functionality will allow for an alternate serial port to be used to support things like UART-based boot and early diagnostic messages until the main console is ready to get activated. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-09Merge tag 'u-boot-imx-20191009' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191009 ------------------- Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532 - MX6UL / ULZ - Toradex board - Allow to set OCRAM for MX6Q/D - MX7ULP - MX8: (container image, imx8mq_mek), SCU API - fix several board booting from SD/EMMC (cubox-i for example) - pico boards [trini: display5 merged manually] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Move WATCHDOG_TIMEOUT_MSECS to Kconfig (Heiko)
2019-10-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Rename existing FSP code to fsp1 - Add fsp2 directory in preparation to support FSP 2.0 - Various x86 platform codes update - Various bug fixes and updates in dm core, sandbox and spl
2019-10-08Merge tag 'u-boot-atmel-2020.01-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features and fixes for 2020.01 cycle The feature set includes support for two new boards from Microchip AT91: The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2 SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor, QSPI, etc The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio, Camera sensor connector, etc. The full support for sam9x60ek will come at a later time. There are still missing bits regarding the clock support and power management controller.
2019-10-08Revert "spl: imx6: Let spl_boot_device return USDHC1 or USDHC2"Adam Ford
Apologies to everyone whose board I broke by attempting to return MMC1 or MMC2. I misunderstood how the MMC indexing worked. This reverts commit 14d319b1856b86e593e01abd0a1e3c2d63b52a8a. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-10-08Revert "imx: mmc_env: update runtime SD/MMC boot env device"Stefano Babic
This reverts commit 34f2feb92db6146831bafa696b7b46785c9f6b10. Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08pico-imx7d: Remove dead code for dm_videoJoris Offouga
Since convert dm_video, unused code introduced, so remove this Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2019-10-08imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08imx: nandbcb: include long help only when enabledParthiban Nallathambi
conditionally include long help text when enabled Signed-off-by: Parthiban Nallathambi <pn@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08misc: imx8: add more scfw apiPeng Fan
Add more scfw api for clk/partition/seco usage The api will be used by ccf/partition/secure boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8: Add support to get container image set sizePeng Fan
To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use flexible offset which is calculated based on the size of the container image generated int the first stage. And pad u-boot.cnt at 1KB alignment. So add code to get the offset when SPL loading u-boot.cnt. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: Add i.MX8MM EVK board support.Peng Fan
Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08arm: dts: add i.MX8MM pin funcPeng Fan
Import i.MX8MM pin func from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08arm: dts: import i.MX8MM dtsiPeng Fan
Import i.MX8MM dtsi from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: soc: probe clock device in arch_cpu_init_dmPeng Fan
Because we need to get cpu freq in print_cpuinfo at very early stage, so we need to make sure the ccm be probed. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: mmc_env: update runtime SD/MMC boot env devicePeng Fan
When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port. To directly return devno, we could avoid add board specific code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add clk support for i.MX8MMPeng Fan
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restructure clock.hPeng Fan
i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: rename clock to clock_imx8mqPeng Fan
i.MX8MQ and i.MX8MM has totally different pll design, so rename clock to clock_imx8mq. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restrict reset_cpuPeng Fan
Make reset_cpu only visible when CONFIG_SYSRESET not defined or CONFIG_SPL_BUILD. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: soc: enable SCTR clock before timer initPeng Fan
To i.MX8MM SCTR clock is disabled by ROM, so before timer init need to enable it. To i.MX8MQ, it does not hurt the clock is enabled again. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: Configure trustzone region 0 for non-secure accessYe Li
Set trustzone region 0 to allow both non-secure and secure access when trust zone is enabled. We found USB controller fails to access DDR if the default region 0 is secure access only. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: Fix MMU table issue for OPTEE memoryPeng Fan
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE memory from its settings. So ARM speculative prefetch in u-boot may access that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory is set to secure access, then the speculative prefetch will fail and cause various memory issue in u-boot. The fail address register and int_status register in trustzone has logged that speculative access from u-boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX8MM PE propertyPeng Fan
i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add pin header for i.MX8MMPeng Fan
Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add get_cpu_rev support for i.MX8MMPeng Fan
There are several variants based on i.MX8MM, add the support in get_cpu_rev Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: update imx-regs for i.MX8MMPeng Fan
i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and register layout change. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: imx-regs: drop unused register definitionsPeng Fan
Drop unused register definitions and structures for i.MX8MQ Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: spl: add spl_board_boot_device for i.MX8MMPeng Fan
Differnet board has different controller used, it is hard to use one layout for them all. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add i.MX8MM cpu typePeng Fan
Add i.MX8MM cpu type and related helper functions Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add IMX8MM kconfig entryPeng Fan
Add IMX8MM kconfig entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add IMX8MQ kconfig entryPeng Fan
Add IMX8MQ kconfig entry, preparing support IMX8MM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add image cfg for i.MX8MM lpddr4Peng Fan
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then we could not reuse imximage.cfg, so create a new one. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: mkimage_fit_atf: Fix FIT image for correct boot orderFrieder Schrempf
Fix the FIT image metadata for i.MX8 to result in the intended boot order (SPL -> ATF -> U-Boot). Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08ARM: imx: arch/arm/mach-imx/spl_qspi.cfgStefan Roese
Similar to "spl_sd.cfg", this patch introduces "spl_qspi.cfg" so that all i.MX6 based boards can use it, when they use SPL and QSPI boot mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
2019-10-08ARM: imx: Add QSPI boot mode for i.MX6UL/ULLStefan Roese
This patch adds the missing boot mode detection for QSPI boot on i.MX6UL/ULL. Without it, booting with SPL from QSPI NOR does not work. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
2019-10-08imx: Kconfig: Reduce default CONFIG_CSF_SIZEBreno Matheus Lima
The default CSF_SIZE defined in Kconfig is too high and SPL cannot fit into the OCRAM in certain cases. The CSF cannot achieve 0x2000 length when using RSA 4K key which is the largest key size supported by HABv4. According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled Devices" it's recommended to pad CSF binary to 0x2000 and append DEK blob to deploy encrypted boot images. As the maximum DEK blob size is 0x58 we can reduce CSF_SIZE to 0x2060 which should cover both CSF and DEK blob length. Update default_image.c and image.c to align with this change and avoid a U-Boot proper authentication failure in HAB closed devices: Authenticate image from DDR location 0x877fffc0... bad magic magic=0x32 length=0x6131 version=0x38 bad length magic=0x32 length=0x6131 version=0x38 bad version magic=0x32 length=0x6131 version=0x38 spl: ERROR: image authentication fail Fixes: 96d27fb218 (Revert "habv4: tools: Avoid hardcoded CSF size for SPL targets") Reported-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-10-08imx: add the i.MX8M reset controller nodePatrick Wildt
This patch adds the reset controller node to the i.MX8MQ SoC device tree. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08imx: add support for i.MX8MQ power domain controllerPatrick Wildt
Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08ARM: dts: pcl063: add usdhc reset pin of eMMCParthiban Nallathambi
pcl063 phycore SoM with eMMC also got usdhc reset pin, add reset pin to pinmux. Signed-off-by: Parthiban Nallathambi <pn@denx.de>
2019-10-08imx: wandboard: convert FEC support to DM_ETHAnatolij Gustschin
Remove CONFIG_DM_ETH conversion warning to avoid board removal. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-10-08dts: imx28: Remove #include "imx28.dtsi" from imx28-u-boot.dtsi fileLukasz Majewski
After this change it is possible to use imx28-<board>-u-boot.dtsi with the imx28-u-boot.dtsi explicitly included without breaking setup from imx28-<board>.dts file. The problem is that the imx28.dtsi included in a wrong place overrides the changes made in imx28-<board>.dts. As a result some devices are "disabled" in the final DTB. Signed-off-by: Lukasz Majewski <lukma@denx.de>
generated by cgit (git 2.34.1) at 2025-01-10 11:27:33 +0000