summaryrefslogtreecommitdiff
path: root/arch/arm
AgeCommit message (Collapse)Author
2019-01-18arm: sunxi: Enable CLK, RESETJagan Teki
CLK and DM_RESET drivers are now available for all of the Allwinner platforms, so enable them in arch/arm/Kconfig Enabling CLK will select DM_RESET by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3Jagan Teki
Update all A80 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. arch/arm/boot/dts/sun9i-a80*: commit 190e3138f9577885691540dca59c2f07540bde04 Merge: cafc87023b0d a7affb13b271 Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 27 14:58:00 2018 +0200 Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt include/dt-bindings/*/sun9i-a80-*: commit 783ab76ae553abc23f80ef7511052d055697531b Author: Chen-Yu Tsai <wens@csie.org> Date: Sat Jan 28 20:22:36 2017 +0800 clk: sunxi-ng: Add A80 Display Engine CCU Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same dts is not available in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18reset: Add Allwinner RESET driverJagan Teki
Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18board: sun50i-h5: Add Emlid Neutis N5 supportAleksandr Aleksandrov
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT module, DDR3 RAM and eMMC. - add neutis-devboard target to dtb makefile - add dtsi file for Neutis N5 needs - add config file for Neutis N5 Dev board Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: update proper commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18sunxi: board: Add i2c initialization for sun50iStefan Mavrodiev
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-16arm: bootm: fix sp detection at end of address rangeSimon Goldschmidt
This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which DRAM bank 'sp' is in. This code failed if a bank was at the end of physical address range (i.e. size + length overflowed to 0). To fix this, calculate 'bank_end' as 'size + length - 1' so that such banks end at 0xffffffff, not 0. Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0") Reported-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2019-01-15am335x: igep003x: Add Device Tree Support and DM_MMC driverEnric Balletbo i Serra
This adds device tree and the DM_MMC driver for the AM335x IGEP based boards. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15am335x: sl50: Add Device Tree Support and DM_MMC driverEnric Balletbo i Serra
This adds device tree and the DM_MMC driver for the SL50 board. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2019-01-15omap3: igep00x0: Add Device Tree Support and DM_MMC driverEnric Balletbo i Serra
This adds device tree for OMAP3 IGEP based boards and the DM_MMC driver. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15arm: dts: Add MMC nodes for HiKey boardManivannan Sadhasivam
Add MMC nodes for HiKey board based on HI6220 SoC. There are three MMC controllers in this SoC, first one used for eMMC, second one used for SD card and third one is not used by u-boot. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-14arm: dts: add ethernet related node for MT7629 SoCWeijie Gao
This patch adds ethernet gmac node for MT7629 with internal gigabit phy. Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14arm: dts: add ethernet related node for MT7623 SoCWeijie Gao
This patch adds ethernet gmac node for MT7623 with MT7530 gigabit switch. Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
2019-01-14reset: MedaiTek: add reset controller driver for MediaTek SoCsWeijie Gao
This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14poplar: add DWC2 OTG gadget supportShawn Guo
It enables DWC2 OTG gadget driver support for Poplar board. As usb2_phy_init() is being always called from board_init(), we can save the call from board_usb_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-11Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2019-01-11Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2019-01-11ARM: dts: socfpga: Add missing SDMMC resetTien Fong Chee
The SDMMC reset is missing from DT, so the reset manager cannot unreset the SDMMC. Add the missing DT reset entry. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-01-10Kconfig: rename CONFIG_SPL_USB_GADGET_SUPPORT as CONFIG_SPL_USB_GADGETJean-Jacques Hiblot
The SPL option for USB gadget should be named after the option for u-boot (CONFIG_USB_GADGET) Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-01-10ARM: dts: define USB aliases for all omap5 platformsJean-Jacques Hiblot
This allows us to properly map the USB controller indexes Tested on dra76 evm, am572 evm Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-01-10Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imxTom Rini
Fixes for 2019.01
2019-01-09imx8m: clock: Fix oscillator valuesFabio Estevam
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return 32768Hz to reflect the reality. This also keeps the values in sync with the Linux clock tree. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-01-09imx8: cpu: correct infoPeng Fan
The CPU banner printed is as following: CPU: CPU: Freescale i.MX8QXP RevB A35 at 147228 MHz 1. Drop the CPU: 2. Change vendor from Freescale to NXP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-09ARM: vf610: ddrmc: do not write CR79 by defaultStefan Agner
The current value CTLUPD_AREF(0) is the reset value of the register, so there is no need to write a value. If needed, the register can be written using board specific CR settings. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-09ARM: vf610: ddrmc: fix initialization completion detectionStefan Agner
The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-09ARM: vf610: ddrmc: fix CR138 preprocessor defineStefan Agner
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask to allow setting PHYDRAM_CK_EN correctly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-09ARM: vf610: ddrmc: program Dummy DDRBYTE1/2Stefan Agner
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter 5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed for correct operation of DDR. Assume the default DDR pin configuration which seems to work well on a Colibri VF50. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-09arm: Round the dma_alloc_coherent memory size to cache line alignedYe Li
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot. The root cause is a cache coherence issue. When it happens, the ctrl_req in gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB controller, any accessing to usb_composite_dev variable will cause the cache line refill, then when setup transfer is completed, reading the setup data in ctrl_req will gets old value from cache not from memory. The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. so it still needs cache maintain operations before/after HW accessing. Since the cache flush or invalidate bases on cache line, so when the allocated memory size is not cache line aligned, potentially it may meet such issue. This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-09sunxi: drop default SPL_LIBDISK_SUPPORT enablementAndre Przywara
There is no code for using partition labels in the Allwinner SPL port. Even so the name is slightly misleading, CONFIG_SPL_LIBDISK_SUPPORT was meant to guard partition code for the SPL. Remove the "imply" line in the Kconfig to make this obvious and avoid unneeded code inclusions, helping to keep the H6 SPL code small. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-06Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini
2019-01-04exynos: Leave the compiler to choose the register to avoid possible r0 ↵Guillaume GARDET
corruption Reported-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-01-03exynos: allow SPL to build in thumb modeGuillaume GARDET
Building peach-pi smdk5420 and peach-pit with thumb mode for SPL ends-up in the following error: Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' Use an intermediate register to be able to use thumb for exynos5 SPL. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-01-02rockchip: rk3399-puma: Set VDD_LOG to 950 mV.Christoph Muellner
This patch sets VDD_LOG to 950 mV on RK3399-Q7. This is required to address stability issues on Puma in heavy-load use-cases. Reported-by: Assaf Agmon <assaf@r-go.io> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02rockchip: rk3399-puma: Cleanup of vdd_log DTS entry.Christoph Muellner
This patch eliminates the non-standard entries "rockchip,pwm_id" and "rockchip,pwm_voltage". They are neither documented nor read out by any driver. Additionally it introduces the entry regulator-init-microvolt and sets it to 900 mV, which is the default target value for VDD_LOG. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02rockchip: rk3036: ram: update licenseKever Yang
All the source code of sdram_rk3036.c are from Rockchip, update the copyright to owned by Rockchip. Because rockchip may use this copy of code both for open source project and internal project, update the license to use both GPL2.0+ and BSD-3 Clause. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02rockchip: sdram-common: fix wrong size for 4GB in 32bit SoCKever Yang
This is workaround for issue we can't get correct size for 4GB ram in 32bit system and available before we really need ram space out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram). The size of 4GB is '0x1 00000000', and this value will be truncated to 0 in 32bit system, and system can not get correct ram size. Rockchip SoCs reserve a blob of space for peripheral near 4GB, and we are now setting SDRAM_MAX_SIZE as max available space for ram in 4GB, so we can use this directly to workaround the issue. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-By: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2019-01-01Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imxTom Rini
imx for 2019.01 - introduce support for i.MX8M - fix size limit for Vhybrid / pico boards - several board fixes - w1 driver for MX2x / MX5x
2019-01-01imx8m: ddr: removed unused macrosPeng Fan
Remove unused DDRC register macros. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: add i.MX8MQ EVK supportPeng Fan
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty NOTICE: BL31: Built : 09:28:54, Nov 8 2018 lpddr4 swffc start NOTICE: sip svc init U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2019-01-01drivers: ddr: introduce DDR driver for i.MX8MPeng Fan
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: add lpddr4 header filePeng Fan
Introduce lpddr4 header file Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: not build bootaux when building SPLPeng Fan
No need to build bootaux in SPL stage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8mq: build flash.binPeng Fan
Build flash.bin for i.MX8MQ, it will include signed hdmi firmware, spl, ddr firmware, fit image(bl31.bin, u-boot-nodtb.bin, dtb). Burn it to 33KB offset of SD card. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: introduce imximage cfg filePeng Fan
imximage.cfg will be used to generate the flash.bin Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: introduce script to generate fit imagePeng Fan
Introduce script to generate fit image for i.MX8M Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: clock refactor dram pll partPeng Fan
Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: spl: add MMC BOOT Device for i.MX8MPeng Fan
Add MMC BOOT Device for i.MX8M Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: rename mx8m,MX8M to imx8m,IMX8MPeng Fan
Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01imx: introduce is_imx8mq helperPeng Fan
Introduce is_imx8mq header macro Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: cpu: add CHIP_REV_2_1 macroPeng Fan
Introduce CHIP_REV_2_1 macro. Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-05 02:16:29 +0000