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2020-07-07Merge tag 'u-boot-stm32-20200707' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - arch and board update for stm32mp15: - use OPP information in device tree for 800MHz/650MHz support - ram: inprovments of test command - solve boot on closed chip when access to DBGMCU_IDC is protected - stm32prog command: Add "device anme" during USB enumeration - update configs: activate WATCHDOG and 'env erase' command, increase teed partition, support SD card after NOR boot by default and use env info in env_check - some sboard cleanups: gpio hog in dh board, specific driver for type-c stusb1600 controller code in a driver move part of code in spl.c and in common directory - fix STM32 compatible for dwc_eth_qos driver - support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx drivers - vrefbuf: fix a possible overshoot when re-enabling
2020-07-07Merge tag 'u-boot-atmel-2020.10-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.10 cycle
2020-07-07arm64: issue ISB after updating system registersVolodymyr Babchuk
ARM Architecture reference manual clearly states that PE pipeline should be flushed after changes to some system registers. Refer to paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI 0487B.a). Failing to issue instruction synchronization barrier can lead to spurious errors, like synchronous exception when accessing FPU registers. This is very prominent on CPUs with long instruction pipeline, like ARM Cortex A72. This change fixes the following U-Boot panic: "Synchronous Abort" handler, esr 0x1fe00000 elr: 00000000800948cc lr : 0000000080091e04 x0 : 00000000801ffdc8 x1 : 00000000000000c8 x2 : 00000000800979d4 x3 : 00000000801ffc60 x4 : 00000000801ffd40 x5 : ffffff80ffffffd8 x6 : 00000000801ffd70 x7 : 00000000801ffd70 x8 : 000000000000000a x9 : 0000000000000000 x10: 0000000000000044 x11: 0000000000000000 x12: 0000000000000000 x13: 0000000000000000 x14: 0000000000000000 x15: 0000000000000000 x16: 000000008008b2e0 x17: 0000000000000000 x18: 00000000801ffec0 x19: 00000000800957b0 x20: 00000000000000c8 x21: 00000000801ffdc8 x22: 000000008009909e x23: 0000000000000000 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000801ffc50 Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0) While executing instruction str q0, [sp, #112] in vsnprintf() prologue. This panic was observed only on Cortex A72 so far. This patch places ISBs on other strategic places as well. Also, this probably is the right fix for the issue workarounded in the commit 45f41c134baf ("ARM: uniphier: add weird workaround code for LD20") Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Suggested-by: Julien Grall <julien.grall.oss@gmail.com> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> CC: Tom Rini <trini@konsulko.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Julien Grall <julien@xen.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07stm32mp1: use the command env info in env_checkPatrick Delaunay
Activate CMD_NVEDIT_INFO and use the new command "env info -d -p -q" to automatically save the environment on first boot. This patch allows to remove the env_default variable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: protect DBGMCU_IDC access with BSECPatrick Delaunay
As debugger must be totally closed on Sec closed chip, the DBGMCU_IDC register is no more accessible (self hosted debug is disabled with OTP). This patch adds a function bsec_dbgswenable() to check if the DBGMCU registers are available before to access them: BSEC_DENABLE.DBGSWENABLE = self hosted debug status. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: stm32prog: add "Device Name" in iproduct during DFU USB ↵Patrick Delaunay
enumeration Add "Device Name" in iproduct during DFU USB enumeration to have this information in STM32CubeProgrammer trace (this tools is compatible with @Name since v2.3) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPLPatrick Delaunay
This patch allows to switch the CPU frequency to 800MHz on the ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM using the STM32MP15x SOC and when it is supported by the HW (for STM32MP15xD and STM32MP15xF). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07board: st: stpmic1: add function stpmic1_initPatrick Delaunay
Add a function stmpic_init to early initialize the PMIC STPMIC1 - keep vdd on during the reset cycle (to avoid issue when backup battery is absent) - Check if debug is enabled to program PMIC according to the bit This patch allows to remove the compilation of spl.c file from stm32mp1 board in dh_stm32mp1. CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier in SPL, in the function board_early_init_f. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: add weak function to save vddcorePatrick Delaunay
Add a weak functions to save the vddcore voltage value provided in the OPP node when the clock tree is initialized. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07ARM: dts: stm32: add cpufreq support on stm32mp15xPatrick Delaunay
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses operating points V2 bindings (no legacy). Nvmem cells have to be used to know the chip version and then which OPPs are available. Note that STM32 cpufreq driver is mainly based on "cpufreq-dt" driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: spl: add bsec driver in SPLPatrick Delaunay
Add the bsec driver in SPL, as it is needed by SOC part number detection to found the supported OPP. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07ARM: dts: rockchip: Add Radxa Rock Pi N8 initial supportJagan Teki
Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3288 SOM need to mount on top of radxa dalang carrier board for making Rock Pi N8 SBC. So, add initial support for Rock Pi N8 by including rk3288, rk3288 vamrc-som and raxda dalang carrier board dtsi files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07ARM: dts: rockchip: Add VMARC RK3288 SOM initial supportJagan Teki
VMARC RK3288 SOM is a standard SMARC SOM design with Rockchip RK3288 SoC, which is designed by Vamrs. Specification: - Rockchip RK3288 - PMIC: RK808 - SD slot, 16GiB eMMC - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet, PCIe - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3288 SOM, this would use with associated carrier board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07ARM: dts: rockchip: radxa-dalang: Update sdmmc propertiesJagan Teki
Radxa dalang carrier boards are used to mount vmarc SoM's of rk3399pro and rk3288 to make complete SBC. Among these combinations, card detection gpio, max-frequency properties are used with rk3399pro SoM but not required for rk3288 SoM based on the hardware schematics. So, let's move these sdmmc specific properties on associate vmarc dtsi to make common use of dalang carrier device tree file. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07rockchip: rk3399: allow deselecting SPL_ATF_NO_PLATFORM_PARAMHugh Cole-Baker
SPL_ATF_NO_PLATFORM_PARAM is selected by default for RK3399 configs, to guard against issues when used with TF-A versions that perform insufficient validation on the platform parameter. However, since commit 8109f738ffa7 "rockchip: increase FDT buffer size" in TF-A, passing a device tree as platform parameter no longer causes problems for upstream TF-A for RK3399. Since SPL_ATF_NO_PLATFORM_PARAM doesn't need to be selected when using upstream TF-A, change the Kconfig option from select to imply. It'll still default to being selected but can be deselected by a user if they know they will be using a compatible version of TF-A. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Walter Lozano <walter.lozano@collabora.com>
2020-07-07arm64: dts: rockchip: Add Radxa Rock Pi N10 initial supportJagan Teki
Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has - VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3399Pro SOM need to mount on top of radxa dalang carrier board for making Rock Pi N10 SBC. So, add initial support for Rock Pi N10 by including rk3399, rk3399pro vamrc-som and raxda dalang carrier board dtsi files. rk3399pro-rock-pi-n10.dts was synced from linux-next v5.7-rc1. Tested - ROCK PI N10 Model B - ROCK PI N10 Model C - Boot from SD Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07ARM: dts: rockchip: Sync v5.7-rc1 Radxa Dalang CarrierJagan Teki
Carrier board often referred as baseboard. For making complete SBC or any other industrial boards, these carrier boards will be used with associated SOMs. Radxa has Dalang carrier board which supports on-board peripherals, ports like USB-2.0, USB-3.0, HDMI, MIPI DSI/CSI, eDP, Ethernet, WiFi, PCIe, USB-C, 40-Pin GPIO header and etc. Right now Dalang carrier board is used with two SBC-variants: Rock Pi N10 => VMARC RK3399Por SOM + Dalang carrier board Rock Pi N8 => VMARC RK3288 SOM + Dalang carrier board(+codec) So add this carrier board dtsi as a separate file in ARM directory, so-that the same can reuse it in both rk3288, rk3399pro variants of Rockchip SOMs. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07arm64: dts: rockchip: Sync v5.7-rc1 VMARC RK3399Pro SOMJagan Teki
VMARC RK3399Pro SOM is a standard SMARC SOM design with Rockchip RK3399Pro SoC, which is designed by Vamrs. Specification: - Rockchip RK3399Pro - PMIC: RK809-3 - SD slot, 16GiB eMMC - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet, PCIe - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3399Pro SOM, this would use with associated carrier board. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07arm64: dts: rockchip: Sync v5.7-rc1 rk3399pro.dtsiJagan Teki
Sync linux-next v5.7-rc1 rk3399pro.dtsi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07rockchip: Pinebook Pro: Fix SPI flash and store env on itPeter Robinson
Some minor fixes for SPI flash on the Pinebook Pro and also default to saving environment to the SPI flash as it's guaranteed to be on board. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (applied with make savedefconfig) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07rockchip: Pinebook Pro: enable rng to provide an entropy sourcePeter Robinson
Enable the rng so UEFI can provide entropy for KASLR Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-01socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA caseTom Rini
Unless we mark the function as 'static inline' it may end up being non-inlined by the compiled and result in duplicate functions. Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
2020-07-01tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCETom Rini
In order to update our <linux/compiler.h> to a newer version that no longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need to convert arch/arm/mach-tegra/ivc.c to the other macros. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-30Merge branch '2020-06-30-minor-TI-board-updates' into nextTom Rini
- Minor updates to some platforms I am the listed maintainer of. Notably this removes the ti814x_evm which stopped building with the PXA MMC migration series (oops) but hasn't been functional in some time.
2020-06-30ti814x: Remove platformTom Rini
The TI814x (DM814x) platform is rather old and in need of a lot of migration work. As much of that work is well past the deadline, remove this platform. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-30Merge tag 'mips-pull-2020-06-29' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next - net: pcnet: cleanup and add DM support - Makefile: add rule to build an endian-swapped U-Boot image used by MIPS Malta EL variants - CI: add Qemu tests for MIPS Malta
2020-06-29spi: Move DM_SPI_FLASH and SPI_FLASH_DATAFLASH to Kconfig (for ls1021aXXX)Lukasz Majewski
This patch moves the CONFIG_DM_SPI_FLASH and CONFIG_SPI_FLASH_DATAFLASH to be defined in Kconfig, not in board specific header file (include/configs/<board>.h). Before this change the CONFIG_DM_SPI_FLASH was not set in .config (so it was not possible to use CONFIG_IS_ENABLED(DM_SPI_FLASH) in SPI DM/DTS converted drivers), but it was set in u-boot.cfg file. Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2020-06-29spi: Move DM_SPI_FLASH to Kconfig (for NXP's ls1043a)Lukasz Majewski
This patch fixes issue with defining the DM_SPI_FLASH in the configs/include/<board.h> instead of enabling this option in Kconfig. The problem is that CONFIG_IS_ENABLED(DM_SPI_FLASH) shows false as there is no DM_SPI_FLASH=y in .config (but the define is set in u-boot.cfg). As a result conversion of DM_SPI_FLASH to using CONFIG_IS_ENABLED() is not working properly. Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2020-06-29spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*Lukasz Majewski
This change allows more fine tuning of driver model based SPI support in SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI support in SPL and TPL via Kconfig option. Before this change it was necessary to use: /* SPI Flash Configs */ #if defined(CONFIG_SPL_BUILD) #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH #undef CONFIG_SPI_FLASH_MTD #endif in the ./include/configs/<board>.h, which is error prone and shall be avoided when we strive to switch to Kconfig. The goal of this patch: Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL). Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must still support non DM driver. Another use case is the conversion of non DM/DTS SPI driver to support DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the distinction is needed in Kconfig (also if SPL version of the driver supports OF_PLATDATA). In the end of the day one would have to support following use cases (in single driver file - e.g. mxs_spi.c): - U-Boot proper driver supporting DT/DTS - U-Boot proper driver without DT/DTS support (deprecated) - SPL driver without DT/DTS support - SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to run full blown DT/DTS) - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained environment with no fitImage and OF_LIBFDT support). Some boards do require SPI support (with DM) in SPL (TPL) and some only have DM_SPI{_FLASH} defined to allow compiling SPL. This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI) and provides corresponding defines in Kconfig. Signed-off-by: Lukasz Majewski <lukma@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [trini: Fixup a few platforms] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-28Merge tag 'u-boot-rockchip-20200628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;
2020-06-27rockchip: rk3188: Fix back to BROM bootAlexander Kochetkov
Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-26arm: imx: Finish migration of CONFIG_CSF_SIZE to KconfigTom Rini
While in most cases CSF_SIZE is handled via Kconfig we have some i.MX8M platforms that set the size based on the now-renamed CONFIG_SECURE_BOOT symbol. Update things so that CSF_SIZE itself depends on IMX_HAB being enabled and provide the default value for i.MX8M family of parts. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Ye Li <ye.li@nxp.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Fixes: d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-06-26arm: imx: Finish migration from CONFIG_SECURE_BOOT to CONFIG_IMX_HABTom Rini
There are a few remaining places where we say CONFIG_SECURE_BOOT rather than CONFIG_IMX HAB. Update these instances. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Eddy Petrișor <eddy.petrisor@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Priyanka Jain <priyanka.jain@nxp.com> Fixes: d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-06-26Convert CONFIG_AT91_GPIO to KconfigTom Rini
This converts the following to Kconfig: CONFIG_AT91_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-26arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan
Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-25bdinfo: arm: Move ARM-specific info into its own fileSimon Glass
We don't really want to have ARM-specific code in a generic file. Create a new arch-specific function to hold it, and move it into that. Make the function weak so that any arch can implement it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25ARM: dts: imx6q-tbs2910: Fix Ethernet regressionFabio Estevam
Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael@walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Soeren Moch <smoch@web.de>
2020-06-25Merge tag 'xilinx-for-v2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.10 Versal: - xspi bootmode fix - Removing one clock from clk driver - Align u-boot memory setting with OS by default - Map TCM and OCM by default ZynqMP: - Minor DT improvements - Reduce console buffer for mini configurations - Add fix for AMS - Add support for XDP platform Zynq: - Support for AES engine - Enable bigger memory test by default - Extend documentation for SD preparation - Use different freq for Topic miami board mmc: - minor GD pointer removal net: - Support fixed-link cases by zynq gem - Fix phy looking loop in axi enet driver spi: - Cleanup global macros for xilinx spi drivers firmware: - Add support for pmufw reloading fpga: - Improve error status reporting common: - Remove 4kB addition space for FDT allocation
2020-06-24topic: zynqmp: Add support for zynqmp-xilinx-xdp platformMike Looijmans
XDP - Xilinx Drone Platform is a board for drones or other UAV. Pinmux the SD card by default, and if the SD card detect line is high (inactive) then pinmux the SD1 interface to EMIO instead. SD is placed on extension card and shares connection with on board wife. That means that when SD card is present in the board wifi can't be used. There seems to be an issue with DDR access from PL at 2400MT/s, after updating the PMU and ATF firmware this is causing extremely slow DDR access. Reducing the DDR speed from 2400 to 2133 appears to solve that issue, even though the hardware has proven to be 2400 capable. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24arm64: zynqmp: Change spi-max-frequency for qspi miniT Karthik Reddy
Change mini u-boot qspi spi-max-frequency to 108Mhz, make the frequency similar to full u-boot qspi flash spi-max-frequency. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24arm64: zynqmp: Fix si570 clock output names and referencesSaeed Nowshadi
Align clock output names with node references. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-23mx6cuboxi: enable MMC and eMMC in DT for SPLWalter Lozano
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliasesYe Li
Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-22ARM: imx: soc: Select default TEXT_BASE for MX7Marek Vasut
Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7Marek Vasut
There are systems where board_early_init_f() is plain empty. Switch the config option from "select" to "imply", to permit user to unset the BOARD_EARLY_INIT_F if it were to be empty. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut
The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-modeFabio Estevam
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-modeFabio Estevam
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Fix the phy-mode accordingly to fix the regression. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1Fabio Estevam
Sync the device tree with 5.8-rc1. It basically contains the following extra kernel commit: commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Author: Russell King <rmk+kernel@armlinux.org.uk> Date: Wed Apr 15 16:44:17 2020 +0100 ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> , which passes the 'qca,clk-out-frequency' property and it is important to specify the correct frequency generated by the AR8035. Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
2020-06-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi into nextTom Rini
- Convert fsl_espi to driver model (Chuanhua) - Enable am335x baltos to DM_SPI (Jagan) - Drop few powerpc board which doesn't have DM enabled (Jagan)
generated by cgit (git 2.34.1) at 2025-01-10 07:58:19 +0000