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2020-01-07imx6: aristainetos: add device tree from linuxHeiko Schocher
Add device trees from Linux in preparation for driver model conversions. device tree files taken from Linux: 71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest" and added SPDX license identifier. Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-07imx6: aristainetos: remove 2b versionHeiko Schocher
remove 2b version of aristainetos board, as it is easier to make the DM / DTS port and introduce the 2b board version again (also some more board version). Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-07imx6: aristainetos: move defines to KconfigHeiko Schocher
move defines, which are already moved to Kconfig out of board config. Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-07imx6: remove aristainetos boardHeiko Schocher
remove not anymore used aristainetos board. Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-03arm: mach-k3: Enable WA for R5F deadlockLokesh Vutla
On K3 devices there are 2 conditions where R5F can deadlock: 1.When software is performing series of store operations to cacheable write back/write allocate memory region and later on software execute barrier operation (DSB or DMB). R5F may hang at the barrier instruction. 2.When software is performing a mix of load and store operations within a tight loop and store operations are all writing to cacheable write back/write allocates memory regions, R5F may hang at one of the load instruction. To avoid the above two conditions disable linefill optimization inside Cortex R5F which will make R5F to only issue up to 2 cache line fills at any point of time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-03arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config toolLokesh Vutla
Update the ddr settings to use the DDR reg config tool rev 0.2.0. This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order to avoid DSS underflow errors. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2020-01-02Merge tag 'u-boot-rockchip-20191231' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix latest mainline kernel for rk3308 - Update rk3288-evb config to suport OP-TEE - Fix for firefly-px30 DEBUG_UART channel and make it standalone - Script make_fit_atf add python3 support - Fix rk3328 timer with correct COUNTER_FREQUENCY - Fix rk3328 ATF support with enable spl-fifo-mode
2020-01-02arch/arm/Kconfig: typo/grammar/punctuation fixesRobert P. J. Day
Various (mostly minor) spelling, grammar and punctuation tweaks for arch/arm/Kconfig. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2019-12-31rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmcKever Yang
Since mmc to sram can't do dma, add patch to prevent aborts transfering TF-A parts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-28Merge tag 'u-boot-imx-20191228' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - Fixes for Nitrogen6x - Fix corruption for mx51evk - colibri i.MX6: fix broken ESDHC conversion - mx6sxsabresd: fix broken mmcdev - imx6q_logic: cleanup boot sequence - update ATF for imx8mq_evk - pfuze: fix pmic_get() Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-27ARM: i.MX6: TARGET_NITROGEN6X: add 'select MX6QDL'Troy Kisky
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata from i.MX6 UP system" for nitrogen6x. The above commit removed the errata for the board since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS This restores the errata configs. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-12-27tools/imximage: share DCD information via KconfigJorge Ramirez-Ortiz
IMX based platforms can have the DCD table located on different addresses due to differences in their memory maps (ie iMX7ULP). This information is required by the user to sign the images for secure boot so continue making it accessible via mkimage. Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-12-27rockchip: add description for TPL_ROCKCHIP_COMMON_BOARDThomas Hebb
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but this one doesn't for some reason. Add a description to make the menu easier to read. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: px30-firefly add standalone dtsKever Yang
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot proper will use the dts setting to do the IOMUX init, and a separate dts is needed for px30-firefly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: make_fit_atf: explicitly use python3Jack Mitchell
On a distribution with no python2 installed and no python->python3 symlink the script will fail to execute. Specify python3 explicitly as it's already a requirement to build u-boot. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: fit_spl_optee: get text and optee base from buildKever Yang
Instead of hardcode the base address, we can get them from the build output, eg. get the SYS_TEXT_BASE from .config and get optee base from DRAM_BASE. We can use this script for SoCs with DRAM base not from 0x60000000(rk3229 and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-18sunxi: remove __packed from struct sunxi_prcm_regHeinrich Schuchardt
struct sunxi_prcm_reg is naturally packed. There is no need to define it as packed. Defining it as packed leads to compilation errors with GCC 9.2.1: CC arch/arm/lib/reloc_arm_efi.o arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: :qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~~~ Remove __packed attribute from struct sunxi_prcm_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-18sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2Diego Rondini
Orangepi Zero Plus 2 is an open-source single-board computer, available in two Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the H5 is already supported. H3 Orangepi Zero Plus 2 has: - Quad-core Cortex-A7 - 512MB DDR3 - microSD slot and 8GB eMMC - Debug TTL UART - HDMI - Wifi + BT - OTG + power supply Sync dts from linux v5.2 commit: "ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry" (sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b) Commit: "ARM: dts: sun8i: h3: Refactor the pinctrl node names" (sha1: a4dc791974e568a15f7f37131729b1a6912f4811) has been avoided as it breaks U-Boot build. Signed-off-by: Diego Rondini <diego.rondini@kynetics.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18sunxi: psci: avoid error address-of-packed-memberHeinrich Schuchardt
Compiling with GCC 9.2.1 leads to build errors: arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~ arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~ Use memcpy() and void* pointers to resolve the problem caused by packing the struct sunxi_cpucfg_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18stm32mp1: remove the imply BOOTSTAGEPatrick Delaunay
This patch is only a temporarily workaround for crash introduced by commit ac9cd4805c8b ("bootstage: Correct relocation algorithm"). The crash occurs because the bootstage struct is not correctly aligned when BOOTSTAGE feature is activated. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18stm32mp1: imply CMD_CLSPatrick Delaunay
Activate by default the command CLS (clear screen); this command used in pxe or sysboot command (DISTRO support) when the "menu background" keyword is present. This patch avoid the warning "Unknown command 'cls'" with extlinux.conf: # Generic Distro Configuration file generated by OpenEmbedded menu title Select the boot mode MENU BACKGROUND /splash.bmp TIMEOUT 20 DEFAULT stm32mp157c-ev1-emmc LABEL stm32mp157c-ev1-emmc KERNEL /uImage FDT /stm32mp157c-ev1.dtb APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200 ... Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf 614 bytes read in 36 ms (16.6 KiB/s) Retrieving file: /splash.bmp 46180 bytes read in 40 ms (1.1 MiB/s) Unknown command 'cls' - try 'help' Select the boot mode 1: stm32mp157c-ev1-sdcard ... Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-13dts: am335x-brsmarc1/xre1: insert phy_id againHannes Schmelzer
commit 3b3e8a37d36e ("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id") did sync with recent linux kernel and replaced therefore the 'phy_id' property with a phy-handle pointing to the mdio. This is OK for linux, but introduces trouble with the already running vxWorks on this target. So this commit here re-inerts the phy_id property beside the phy-handle property to be compatible with both. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-12-09ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCsSuman Anna
The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP") added the core logic to update the kernel device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx family of SoCs. The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though provide a higher performance and can run at a higher clock frequency of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the correct clock rates on these SoCs. Note that this higher clock rate is not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or AM574x SoCs) that follow the ABZ package. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-09Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini
2019-12-09arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodesVignesh Raghavendra
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking up on J721e EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09arm: dts: armada-cp110-*dtsi: add xmdio nodesNevo Hed
Based on upstream-linux See https://github.com/torvalds/linux/commit/f66b2aff. However made the XSMI register window 0x16 (22) bytes per my reading of the functional spec. Similar commits in Marvels own repo bump it to 0x200 (512) bytes but I did not see the reasoning for that. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4. Also added device-name attributes to prevent ambiguity in the `mdio` command. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxidGrygorii Strashko
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with internal RX delay provided by the PHY, the MAC will add an TX delay in this case. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: Always build the string_to_enetaddr() helperJoe Hershberger
Part of the env cleanup moved this out of the environment code and into the net code. However, this helper is sometimes needed even when the net stack isn't included. Move the helper to lib/net_utils.c like it's similarly-purposed string_to_ip(). Also rename the moved function to similar naming. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Ondrej Jirman <megous@megous.com>
2019-12-09arm: -march=armv5t for ARM11Heinrich Schuchardt
In GCC 9 support for the Armv5 and Armv5E architectures (which have no known implementations) has been removed, cf. https://gcc.gnu.org/gcc-9/changes.html Commit 16540d07fd62 ("arm: fix -march for ARM11") changed the value of the compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for ARM11. The values prior to this patch were: arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t The change lead to a regression with the Raspberry Pi Zero W not booting anymore. Use -march=armv5t both for ARM1136 and ARM1176. Fixes: 16540d07fd62 ("arm: fix -march for ARM11") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Joris Offouga <offougajoris@gmail.com>
2019-12-09Merge tag 'u-boot-imx-20191209' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support
2019-12-09imx8m: fix rom version check to unbreak some B0 chipsPatrick Wildt
Recently the version check was improved to be able to determine that we're running on SoC revision 2.1. A check for B0 was tightened so that it now must equal 0x20 instead of being bigger than 0x20. On some B0 chips the value returned is 0x1020 instead of 0x20. This means even though it's B0, the check will fail and code relying on the correct chip revision will make wrong decisions. There is no documentation of those bits, but it seems that NXP always uses a byte to encode the revision. Thus remove the upper bits to fix the regression. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-12-06Merge tag 'u-boot-rockchip-20191206' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs
2019-12-06ARM: imx: vining2000: Repair PCIe supportMarek Vasut
Ever since the conversion to DM PCI, the board was missing the PCIe DT nodes, hence the PCI did not really work. Fill in the DT nodes and add missing PCIe device reset. Moreover, bring the PCIe power domain up before booting Linux. This is mandatory to keep old broken vendor kernels working, as they do not do so and depend on the bootloader to bring the power domain up. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-12-06ARM: imx: vining2000: Convert to SPL frameworkMarek Vasut
In preparation for use of DDR DRAM fine-tuning upon boot, convert the board to SPL framework instead of using DCD tables to bring up DRAM and pinmux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-12-06ARM: mx6: pmu: Expose PMU LDO configuration interfaceMarek Vasut
Make the PMU LDO configuration interface available to board code, so that board code can reconfigure the internal LDOs of the SoC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Eric Nelson <eric@nelint.com>
2019-12-06board: colibri_imx7: reserve DDR memory for Cortex-M4Igor Opaniuk
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Use the linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-12-06mx6: Allow configuring the NoC registers on i.MX6QPFabio Estevam
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize. Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2019-12-06mx7ulp: Sync the device tree related filesFabio Estevam
Sync the mx7ulp device tree related files with the one from NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0). The mainline support for i.MX7ULP is very premature at this stage. We should probably re-sync with mainline Linux dts when it gets in better shape, but for now sync with the U-Boot vendor code. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06mx7ulp: scg: Remove unnused scg_a7_apll_init()Fabio Estevam
scg_a7_apll_init() is not called anywhere, so remove such dead code Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitionsFabio Estevam
The LDOVL definitions is common to all the modes, not only RUN mode, so in order to avoid confusion, remove the _RUN notation from the PMC1 LDOVL definitions. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE optionFabio Estevam
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards designed to operate with LDO enabled mode can work with 0.95V at LDO output in RUN mode as per the datasheet. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06mx7ulp: Print the LDO mode statusFabio Estevam
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode or LDO bypass mode. Print the LDO mode status in the U-Boot log for convenience. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06arm: rockchip: rk3308: Initialize the iomux configurationDavid Wu
When we want to use plus pinctrl feature, we need to enable them at spl. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06pwm: rk_pwm: Make PWM driver to support all Rockchip SocsDavid Wu
This PWM driver can be used to support pwm functions for on all Rockchip Socs. The previous chips than RK3288 did not support polarity, and register layout was different from the RK3288 PWM. The RK3288 keep the current functions. RK3328 and the chips after it, which can support hardware lock, configure duty, period and polarity at next same period, to prevent the intermediate temporary state. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CCDavid Wu
The Firefly ROC_RK3308_CC use ref_clock of input mode, and rmii pins of m1 group. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06arm: dts: Add mac node for rk3308 at dtsi levelDavid Wu
The rk3308 only support RMII mode, and if it is output clock mode, better to use ref_clk pin with drive strength 12ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05rockchip: misc: protect serial# from getting overwrittenHeiko Stuebner
serial# is one of the vendor properties and thus protected from being overwritten if already set. If env_set is called anyway this result in some nasty warnings, so check for presence before trying that. In the same direction check for the presence of cpuid# and compare it to the actual hardware and emit a warning if they don't match. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05rockchip: misc: don't fail if eth_addr already setHeiko Stuebner
rockchip_setup_macaddr() runs from an initcall, so returning an error code will make that initcall fail thus breaking the boot process. And if an ethernet address is already set this is definitly not a cause for that, so just return success in that case. Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid"); Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05rockchip: px30: Add support for using UART3 as debug UARTPaul Kocialkowski
Some generic PX30 SoMs found in the wild use UART3 as their debug output instead of UART2 (used for MMC) and UART5. Make it possible to use UART3 as early debug output, with the associated clock and pinmux configuration. Two sets of output pins are supported (M0/M1). Future users should also note that the pinmux default in the dts is to use the M1 pins while the Kconfig option takes M0 as a default. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to CONFIG_DEBUG_UART_CHANNELPaul Kocialkowski
UART3 also has two sets of pins that can be selected. Rename the config option to a common name, to allow it to be used for both UART2 and UART3. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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