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2018-07-12arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan
Add do_bridge_reset() function for Arria 10, it is required by misc.c. arch/arm/mach-socfpga/built-in.o: In function `do_bridge': arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' make[1]: *** [u-boot] Error 1 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan
Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan
Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan
Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Restructure the SPL fileLey Foon Tan
Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan
Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan
Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan
Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan
Move bridge command to misc common driver, in preparation to used by other platforms. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-10board: arm: Add support for Broadcom BCM7445Thomas Fitzsimmons
Add support for loading U-Boot on the Broadcom 7445 SoC. This port assumes Broadcom's BOLT bootloader is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader, loaded as an ELF program by BOLT. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Florian Fainelli <f.fainelli@gmail.com>
2018-07-09reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan
Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET, so can use CONFIG_IS_ENABLED(DM_RESET) checking in reset.h later. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-09arm: dts: bubblegum_96: Enable UART5 for serial consoleManivannan Sadhasivam
This commit enables UART5 found in S900 SoC for serial console support. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09arm: dts: s900: Add UART nodeManivannan Sadhasivam
This commit adds UART node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09clk: Add Actions Semi OWL clock supportManivannan Sadhasivam
This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-09arm: dts: s900: Add Clock Management Unit (CMU) nodesManivannan Sadhasivam
This commit adds Clock Management Unit (CMU) nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09board: Add uCRobotics Bubblegum-96 board supportManivannan Sadhasivam
This commit adds uCRobotics Bubblegum-96 board support. This board is one of the 96Boards Consumer Edition platform based on Actions Semi S900 SoC. Features: - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) - 2GiB RAM - 8GiB eMMC, uSD slot - WiFi, Bluetooth and GPS module - 2x Host, 1x Device USB port - HDMI - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons U-Boot will be loaded by ATF at EL2 execution level. Relevant driver support will be added in further commits. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09arm: Add support for Actions Semi OWL SoC familyManivannan Sadhasivam
This commit adds Actions Semi OWL SoC family support with S900 as the first target SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-03Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-07-03arm: timer: sunxi: add Allwinner timer erratum workaroundAndre Przywara
The Allwinner A64 SoCs suffers from an arch timer implementation erratum, where sometimes the lower 11 bits of the counter value erroneously become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and backwards, with the latter one often showing weird behaviour. Port the workaround proposed for Linux to U-Boot and activate it for all A64 boards. This fixes crashes when accessing MMC devices (SD cards), caused by a recent change to actually use the counter value for timeout checks. Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput in the sunxi_mmc driver") [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Andreas Färber <afaerber@suse.de> Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03arm: timer: factor out FSL arch timer erratum workaroundAndre Przywara
At the moment we have the workaround for the Freescale arch timer erratum A-008585 merged into the generic timer_read_counter() routine. Split those two up, so that we can add other errata workaround more easily. Also add an explaining comment on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Andreas Färber <afaerber@suse.de> Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-02board/aries: RemoveTom Rini
The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-06-30Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2018-06-30mx5: Select ARM_CORTEX_A8_CVE_2017_5715Fabio Estevam
On a 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53 to fix the problem. With this patch applied the kernel reports: CPU0: Spectre v2: using BPIALL workaround Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-29ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for ↵Nishanth Menon
CVE-2017-5715 Enable CVE-2017-5715 option to set the IBE bit. This enables kernel workarounds necessary for the said CVE. With this enabled, Linux reports: CPU0: Spectre v2: using BPIALL workaround This workaround may need to be re-applied in OS environment around low power transition resume states where context of ACR would be lost (off-mode etc). Signed-off-by: Nishanth Menon <nm@ti.com>
2018-06-29ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to ↵Nishanth Menon
facilitate CVE_2017-5715 WA in OS Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr function to setup the bits, we are able to override the settings. Without this enabled, Linux kernel reports: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable With this enabled, Linux kernel reports: CPU0: Spectre v2: using ICIALLU workaround NOTE: This by itself does not enable the workaround for CPU1 (on OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches. Signed-off-by: Nishanth Menon <nm@ti.com>
2018-06-29ARM: Introduce ability to enable invalidate of BTB with ICIALLU on ↵Nishanth Menon
Cortex-A15 for CVE-2017-5715 As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-29ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715Nishanth Menon
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally for BPIALL to be functional on Cortex-A8 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-29usb: sunxi: Use proper reg_mask for clock gate, resetJagan Teki
Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG. unfortunately these are fixed due to lack of separate clock, reset drivers. Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2. This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller. We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-29sunxi: Fix USB PHY index for H3Jagan Teki
This patch update the USB PHY index for Allwinner H3. Same change[1] initially sent, by 'Chen-Yu Tai' but missed to apply due to recursive version changes on the same series. [1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-27Merge git://git.denx.de/u-boot-imxTom Rini
2018-06-27imx6ul: geam: Fix fdt_file mismatchJagan Teki
fdt_file is looking for imx6ul-geam-kit.dtb but Linux has imx6ul-geam.dtb, since Linux skipped -kit on file name by below commit. "ARM: dts: imx6ul-geam: Skip suffix -kit from dts name" (sha1: 182de5ebce71e469cfa686fcdf08c9cbe11ece97) So, due to this mismatch U-Boot failed to pick the proper dtb which eventually break the Linux boot. This patch fixed this mismatch by - renaming dts files - update config option to use new dtb file - update fdt_file to new dtb file name Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-27arm: dts: imx7: colibri: add raw NAND supportStefan Agner
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27arm: dts: imx7: sync with LinuxStefan Agner
Sync with Linux commit 60cc43fc8884 ("Linux 4.17-rc1"). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-23ARM: dts: uniphier: enable SD card for PXs3 reference boardMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-23ARM: dts: uniphier: sync DT with Linux 4.18-rc1Masahiro Yamada
Now that the clock-frequency information has been moved to the driver, more DT sync is possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-21Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2018-06-19meson: use the clock driverBeniamino Galvani
Use the clk framework to initialize clocks from drivers that need them instead of having hardcoded frequencies and initializations from board code. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19clk: add Amlogic meson clock driverBeniamino Galvani
Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19configs: dragonboard410c: remove env partition offsetRamon Fried
BOOT2 is not partitioned, no need for partition offset. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-06-19common: Fix cpu nr type which is always unsigned typeMichal Simek
cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-19ARM: image: Add option for ignoring ep bit 3Marek Vasut
Add option to the booti_setup() which indicates to it that the caller requires the image to be relocated to the beginning of the RAM and that the information whether the image can be located anywhere in RAM at 2 MiB aligned boundary or not is to be ignored. This is useful ie. in case the Image is wrapped in another envelope, ie. fitImage and not relocating it but moving it would corrupt the envelope. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Chen <bin.chen@linaro.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-By: Bin Chen <bin.chen@linaro.org>
2018-06-19ARM: dts: rmobile: Add HS200 support to E3 EbisuMarek Vasut
Add regulator nodes and pinmux settings to the SDHI3 on E3 Ebisu and enable HS200 mode on it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-19ARM: dts: rmobile: Move the PHY reset GPIOs into PHY nodesMarek Vasut
Both the RAVB and SH ether driver now support parsing the PHY reset GPIOs from both the PHY nodes and the MAC nodes, move the reset GPIOs back into the PHY nodes to minimize DT difference between U-Boot and Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-19ARM: dts: rmobile: Move the PHY reset GPIO backMarek Vasut
The current state of RAVB driver expects the PHY reset GPIO in the RAVB mode, move it back from the PHY node to avoid breakage. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-18arm: mach-omap2/omap3/clock.c: Enable all GPIO with CMD_GPIOAdam Ford
When CMD_GPIO is enabled the command 'gpio status -a' can cause a hang or reboot if GPIO banks are not enabled, because it scans all banks. This patch enables all GPIO banks so 'gpio status -a' can fully execute. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-06-18arm: Do not clear LR on exception in SPLAndrew F. Davis
When an exception or interrupt occurs the link register (LR) may contain the source of the exception, although we do not print the value it may still be extracted with a debugger. When in SPL we loop on getting and exception, but use a linking branch, which over-writes the LR value, use a regular branch instruction here. Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-06-18.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignoreMasahiro Yamada
Follow Linux commit 10b62a2f785a (".gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-18dm: gpio: Add DM compatibility to GPIO driver for DavinciAdam Ford
This adds DM_GPIO support for the davinici GPIO driver with DT support. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-06-18db410c: fix alignment of dts fileRamon Fried
Alignment was wrong, missing one tab. fix it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
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