summaryrefslogtreecommitdiff
path: root/arch/arm
AgeCommit message (Collapse)Author
2019-05-08rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1Jagan Teki
Add u-boot,dm-pre-reloc property for spi1, so-that the subsequent rk3399 boards which boot from SPI. This help to separate the u-boot specific properties away from base dts files so-that the Linux sync become easy and meaningful. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi filesJagan Teki
Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08dts: Makefile: Build rockchip dtbs based on SoC typesJagan Teki
- Sometimes u-boot specific dtsi files are included automatically which would build for entire rockchip SoC, even-though the respective dtsi should used it for specific family of rockchip SoC. - Sometimes u-boot specific dts nodes or properties can use config macros from respective rockchip family include/configs files, example CONFIG_SPL_PAD_TO. So, it's better to compile the dtbs based on the respective rockchip family types rather than rockchip itself to avoid compilation issues. This patch organize the existing dtb's based on the rockchip family types. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: chromebook_minnie: Enable soundSimon Glass
Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3399: add tpl supportKever Yang
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add u-boot-tpl-v8.ldsKever Yang
We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08rockchip: px5: add timer0 dts node as tick timerKever Yang
Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3368: remove uart iomux init in SPLKever Yang
The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL onlyKever Yang
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5 update dts for spl/tplKever Yang
TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk3368: support UART2/4 in board_debug_uart_init()Kever Yang
evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk322x: dts: enable uart2 for SPL/TPLKever Yang
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08sysreset: enable driver support in SPL/TPLKever Yang
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add tpl supportKever Yang
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add a separate stack for TPLKever Yang
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add option for TPL support in arm 32bitKever Yang
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: remove ARCH_ROCKCHIP macro in common codeKever Yang
This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add common header boot0.h and gpio.h for socKever Yang
boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- RZ/A1 addition. - Old board removal.
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Assorted stratix10 fixes. - DDR driver DM migration.
2019-05-07ARM: dts: renesas: Add RZ/A1 GR-Peach boardChris Brandt
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07ARM: dts: renesas: Add RZ/A1 platform codeChris Brandt
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various pinctrl / gpio fixes for R-Car
2019-05-06ARM: socfpga: stratix10: Probe FPGA status before bridge enableAng, Chee Hong
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure Device Manager (SDM) to get the status of FPGA and make sure the FPGA is in user mode before enable the bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-05-06ARM: socfpga: stratix10: Disable FPGA2SOC resetAng, Chee Hong
Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-05-06arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06arm: dts: Stratix10: Add SDRAM nodeLey Foon Tan
Add SDRAM device tree node. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-05arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36Brad Griffis
for suspend/resume robustness update value for ext_phy_ctrl_36 for suspend/resume robustness with hardware leveling enabled. Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw levelingBrad Griffis
In case of RTC+DDR resume, need to restore EMIF context before initiating hardware leveling. Signed-off-by: Brad Griffis <bgriffis@ti.com> [j-keerthy@ti.com Fixed the am335x build issues] Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr pathBrad Griffis
Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 errorBrad Griffis
Add 1ms delay to avoid L3 timeout error during suspend resume. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and ↵Brad Griffis
EXT_PHY_CTRL1_SHADOW Adjust DQS skew in case where invert_clkout=1 is used. Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05spl: fix linker size check off-by-one errorsSimon Goldschmidt
This fixes SPL linker script size checks for 3 lds files where the size checks were implemented as "x < YYY_MAX_SIZE". Fix the size checks to be "x <= YYY_MAX_SIZE" instead. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-05configs: socfpga: add imply pl310 cache controllerDinh Nguyen
Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05ARM: socfpga: use the pl310 driver to configure the cacheDinh Nguyen
Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05ARM: pl310: Add macro's for handling tag and data latency maskDinh Nguyen
Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05arch: armv8: Provide a way to disable cache maintenance opsVignesh Raghavendra
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache maintenance operations being done to support non-coherent platforms causes issues. For example, here is how U-Boot prepares/handles a buffer to receive data from a device (DMA Write). This may vary slightly depending on the driver framework: Start DMA to write to destination buffer Wait for DMA to be done (dma_receive()/dma_memcpy()) Invalidate destination buffer (invalidate_dcache_range()) Read from destination buffer The invalidate after the DMA is needed in order to read latest data from memory that’s updated by DMA write. Also, in case random prefetch has pulled in buffer data during the “wait for DMA” before the DMA has written to it. This works well for non-coherent architectures. In case of coherent architecture with L3 cache, DMA write would directly update L3 cache contents (assuming cacheline is present in L3) without updating the DDR memory. So invalidate after “wait for DMA” in above sequence would discard latest data and read will cause stale data to be fetched from DDR. Therefore invalidate after “wait for DMA” is not always correct on coherent architecture. Therefore, provide a Kconfig option to disable cache maintenance ops on coherent architectures. This has added benefit of improving the performance of DMA transfers as we no longer need to invalidate/flush individual cache lines(especially for buffer thats several KBs in size). In order to facilitate use of same Kconfig across different architecture, I have added the symbol to top level arch/Kconfig file. Patch currently disables cache maintenance ops for arm64 only. flush_dcache_all() and invalidate_dcache_all() are exclusively used during enabling/disabling dcache and hence are not disabled. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-05-04ARM: rmobile: Always select pin control drivers on Gen3Marek Vasut
To assure the pins on R-Car Gen3 SoCs are configured correctly, always select pin control drivers on Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROLRobert P. J. Day
>From way back in 2015: commit dffb86e468c8e02ba77283989aefef214d904dc5 Author: Masahiro Yamada <yamada.masahiro@socionext.com> Date: Wed Aug 12 07:31:54 2015 +0900 of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-05-04arm: davinci: remove leftover code for dm* SoCsBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped a while ago. There's still a lot of leftover code in mach-davinci though. Entirely remove certain files and modify the common code to no longer reference unsupported chips. Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX but not all define SOC_DA850 (e.g. omapl138). We can safely remove all ifdefs for the former, but let's leave the ones for the latter. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04arm: davinci: remove dead code for PHYs used by DaVinci DM* boardsBartosz Golaszewski
The support for DaVinci DM* boards has been dropped a while ago. The code for all those PHYs is no longer used and they have their own proper PHY drivers in drivers/net/phy anyway. Remove all dead code. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-03Merge git://git.denx.de/u-boot-socfpgaTom Rini
- Misc MMC, FPGA bridge, general SoCFPGA fixes
2019-05-03Merge git://git.denx.de/u-boot-usbTom Rini
- DaVinci updates
2019-05-03Merge git://git.denx.de/u-boot-marvellTom Rini
- Fix in kwbimage (return code checking) (Young Xiao) - Misc updates to Turris Omnia (Marek)
2019-05-03ARM: davinci: Remove unused functions from headerAdam Ford
There are a few functions defined in the header file, but they are not referenced by any Davinci code. In order to make a general function in the future with static function declarations, this patch will remove the references all together. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-03Merge branch '2019-05-03-master-imports'Tom Rini
- Various btrfs fixes - Various TI platform fixes - Other fixes (cross build, taurus update, Kconfig help text)
2019-05-03ARM: dts: logicpd-som-lv: Fix MMC1 card detectAdam Ford
The card detect pin was incorrectly using IRQ_TYPE_LEVEL_LOW instead of GPIO_ACTIVE_LOW when reading the state of the CD pin. Without this patch, MMC1 won't be detected. This is the same patch submitted to linux-omap, but I was hoping to get it applied to U-Boot without having to wait for the linux adoption and then backporting. Fixes: 5448ff33f281 ("ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4") Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-03ti: Add device-tree for am335x-pocketbeagle.Vagrant Cascadian
Add device-tree files from linux 5.1-rc7 needed to complete support for PocketBeagle. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-03arm: dts: k3-am654: Sync IOPAD macros with LinuxAndreas Dannenberg
Transition to the IOPAD macros as used in Linux in which the pin mux mode is specified using a dedicated parameter while also dropping the related MUX_MODEx macros that are no longer needed. This transition will allow us to keep both Linux and U-Boot DTS in sync more easily. While at it also align the file name of the include file itself and update any references accordingly. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit (git 2.34.1) at 2024-12-26 20:37:03 +0000