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2020-07-28rockchip: Drop the fit_spl_optee.sh scriptSimon Glass
Now that all board use binman instead of this script, drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28rockchip: Convert evb-rk3288 over to use binmanSimon Glass
At present this board uses a custom script to produce the .its file. Update it to use binman instead. Binman can create all the images that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28mediatek: Makefile: Drop explicit targets built by binmanSimon Glass
On mediatek various files that need to be created by binman. It does not make sense to enumerate these in the Makefile. They are described in the configuration (devicetree) for each board and we can simply run binman (always) to generate them. This avoid sprinkling the Makefile with arch-specific code. Also update the binman definition so that idbloader.img is only needed when SPL is actually being used. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28Makefile: Rename ALL-y to INPUTS-ySimon Glass
When binman is in use, most of the targets built by the Makefile are inputs to binman. We then need a final rule to run binman to produce the final outputs. Rename the variable to indicate this, and add a new 'inputs' target. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28tegra: Don't enable binman on ARMv8 SoCsSimon Glass
At present only the ARMv7 tegra SoCs actually use binman to create an image. Change the config to reflect this, since otherwise running binman will produce an error. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28rockchip: Enable building a SPI ROM image on bobSimon Glass
Add a simple binman config and enable CONFIG_HAS_ROM so that U-Boot produces a ROM for bob. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28rockchip: Enable building a SPI ROM image on jerrySimon Glass
Add a simple binman config and enable CONFIG_HAS_ROM so that U-Boot produces a ROM for jerry. Change the binman image definition to support multiple images, since it may be used to build both u-boot-rockchip.bin and u-boot.rom Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28rockchip: Allow Bob to use SPI bootSimon Glass
Bob is a Chromebook and can boot from SPI flash. Add it to the condition check for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28Convert CONFIG_ENV_OVERWRITE to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a - lx2-watchdog support - layerscape: pci-endpoint support, spin table relocation fixes and cleanups - fsl-crypto: RNG support and bug fixes
2020-07-27Merge tag 'dm-pull-20jul20-take2a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-dm binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-27arm: dts: ls1028a: Add dspi flash device node to qdsZhao Qiang
Add dspi flash device node to fsl-ls1028a-qds.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27arm64: lx2160a: dts: Add watchdog nodeZhao Qiang
Add watchdog node which is sbsa into lx2160a dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: dts: ls1046a: Add the PCIe EP nodeXiaowei Bao
Add the PCIe EP node for ls1046a. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27arm: dts: lx2160a: Increase configuration window sizeWasim Khan
lx2160a rev2 requires 4KB space for type0 and 4KB space for type1 iATU window. Increase configuration size to 8KB to have sufficient space for type0 and type1 window. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27arm64: ls1043a: Remove the workaround of erratum A-009929Hou Zhiqiang
The workaround has been implemented in PBI phase, so remove the duplicated implementation from U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: dts: fsl-lx2160a: add flash node under dspi to qds dtsZhao Qiang
Add flash node under dspi into fsl-lx2160a-qds.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27I2C: ls1043a, ls1046a: enable SYS_I2C_MXCBiwen Li
This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: rework spin tableMichael Walle
There are two issues: (1) The spin table doesn't convert the endianness of the jump address. Although there is code for it, the result isn't used at all (x0). (2) If something goes wrong, the function returns. But that doesn't make sense at all. Use the actual converted jump address as destination to fix. If there is an error, jump to a trap loop. And rearrange the code exception level switching code to make it smaller and clearer. This reduces the size of the spin table code section from 696 bytes to 424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696 bytes to 632 bytes. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: relocate spin table if EFI_LOADER is enabledMichael Walle
On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: clean exported symbols in spintable.SMichael Walle
Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: drop first .ltorg directive in spintable.SMichael Walle
Now that the spin table is in a separate module, this is no longer necessary. Drop it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: make wake_secondary_core_n() staticMichael Walle
This function is not used outside the module. Make it static. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: simplify get_spin_tbl_addr() callsMichael Walle
There is no need to cast around. Assign the address to the local variable and use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: remove determine_mp_bootpg()Michael Walle
Only the PowerPC architecture needs this function. Remove it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: fix alignment for spin tableMichael Walle
Fix the alignment so it will match the comments. The spin table has to be 8 byte aligned, so ".align 3" is enough. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: load function pointer using ADRMichael Walle
Don't use LDR to load a pointer to a function. This will generate a literal which cannot be relocated. Use ADR which is PC-relative and therefore can easily be relocated. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: move spin table into own moduleMichael Walle
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary CPUs are brought up in main u-boot. This will make it possible to only compile the spin table code for the main u-boot and omit it in SPL. This saves about 720 bytes in the SPL. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: properly use CPU_RELEASE_ADDRMichael Walle
The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: pretty print info about SMP coresMichael Walle
Make the print of the starting address a debug output and pretty print the info about online cores. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: fix spin-table supportMichael Walle
Spin tables are broken with bootefi. This is because - in contrast to the booti call chain - there is no call to smp_kick_all_cpus(). Due to this missing call the secondary CPUs are never released from their "wait for interrupt state", see secondary_boot_func() in lowlevel.S. Originally, this "wait for interrupt" is there to make sure, the spin table is cleared before the secondary cores read it for the first time. But the boot flow for the layerscape architecture is different from that. The CPUs are release from their BootROM _after_ U-Boot's spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c. Thus, there is no need to wait for this interrupt and no need for kicking all cores on cpu_release. An atomic 64bit write to the spin-table and a "sev" is sufficient. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscapehui.song
Enable the gpio feature on fsl-layerscape platform. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: gpio: add gpio featurehui.song
add one struct mpc8xxx_gpio_plat to enable gpio feature. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: ls1028a: move FSL_LAYERSCAPE to kconfigMichael Walle
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-25treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25arm: mach-k3: Use SOC driver for device identificationDave Gerlach
Make use of UCLASS_SOC to find device family and revision for print_cpuinfo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25arm: dts: k3-j721e-mcu-wakeup: Introduce chipid nodeDave Gerlach
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25arm: dts: k3-am65-wakeup: Introduce chipid nodeDave Gerlach
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev KitAdam Ford
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also known as the RZ/G2M. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1Adam Ford
This patch imports the device tree and required bindings to permit the device tree to build for the R8Z774A1 (RZ/G2M). Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25ARM: renesas: Add basic R8A774A1 SupportAdam Ford
In order to build boards based on the R8A774A1, there needs to be a config option from which to enable other drivers and/or flags for this SoC. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-23Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini
binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-22arm64: dts: rockchip: Add u-boot, spl-boot-order for ROCKPi N10Jagan Teki
Add u-boot,spl-boot-order for ROCKPi N10, so-that it can able to boot from eMMC and SDMMC in order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add PCIe for RockPI N10Jagan Teki
This patch adds support to enable PCIe for RockPI N10. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm: dts: rockchip: Add HDMI out for RockPI N8/N10Jagan Teki
This patch adds support to enable HDMI out for N10 and N8 combinations SBCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Add USB for RockPI N8/N10Jagan Teki
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0 ports. This patch adds support to enable all these USB ports for N10 and N8 combinations SBCs. Note that the USB 3.0 port on RockPI N8 combination works as USB 2.0 OTG since it is driven from RK3288. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Add usb host0 ohci node for rk3288Jagan Teki
rk3288 and rk3288w have a usb host0 ohci controller. Although rk3288 ohci doesn't actually work on hardware, but rk3288w ohci can work well. So add usb host0 ohci node in rk3288 dtsi and the quirk in ohci platform driver will disable ohci on rk3288. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm: dts: rockchip: Sync rk3288 dtsi from linuxSuniel Mahesh
This sync has changes required to use HDMI CEC pin in U-Boot. Sync dts from linux v5.8-rc5 commit: "ARM: dts: rockchip: define the two possible rk3288 CEC pins" (sha1: 838980dd04e994bf81cf104fa01ae60802146b39) Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from LinuxJagan Teki
Sync ROCKPi N8/N10 dts(i) changes from Linux. commit <afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support") Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-01-29 20:49:28 +0000