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2019-03-09ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3NEugeniu Rosca
v2019.01 commit cbff9f80cedd ("ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi. Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is equivalent to partially reverting below v2019.01 commits: - f529bc551b6d ("ARM: dts: rmobile: Extract USB nodes on M3N") - 830b94f76867 ("ARM: dts: rmobile: Extract SDHI nodes on M3N") Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously: - not needed if no U-boot-specific changes are needed in those nodes. - potentially dangerous/error-prone, since the duplicated properties override the properties originally defined in <soc>.dtsi. One possible consequence is that <soc>.dtsi is getting an update from Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation, the obsolete property values from <soc>-u-boot.dtsi will take precedence masking some of the <soc>.dtsi updates, potentially leading to all kind of obscure issues. Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user" of r8a77965-u-boot.dtsi) before and after the patch (slightly reformatted to avoid 'git am/apply' issues and to reduce the width). What below output means is there is already a mismatch in some of SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in r8a77965-u-boot.dtsi. $> dtdiff before-r8a77965-salvator-x-u-boot.dtb \ after-r8a77965-salvator-x-u-boot.dtb --- /dev/fd/63 2019-03-09 12:57:40.877963983 +0100 +++ /dev/fd/62 2019-03-09 12:57:40.877963983 +0100 @@ -1471,7 +1471,7 @@ bus-width = <0x4>; cd-gpios = <0x51 0xc 0x1>; clocks = <0x6 0x1 0x13a>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa5 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x4d>; @@ -1492,7 +1492,7 @@ sd@ee120000 { clocks = <0x6 0x1 0x139>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa6 0x4>; max-frequency = <0xbebc200>; power-domains = <0x1 0x20>; @@ -1504,7 +1504,7 @@ sd@ee140000 { bus-width = <0x8>; clocks = <0x6 0x1 0x138>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; fixed-emmc-driver-type = <0x1>; interrupts = <0x0 0xa7 0x4>; max-frequency = <0xbebc200>; @@ -1526,7 +1526,7 @@ bus-width = <0x4>; cd-gpios = <0x5a 0xf 0x1>; clocks = <0x6 0x1 0x137>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa8 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x56>; @@ -1868,14 +1868,14 @@ usb-phy@ee0a0200 { #phy-cells = <0x0>; - clocks = <0x6 0x1 0x2be>; + clocks = <0x6 0x1 0x2bf>; compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy"; phandle = <0x47>; pinctrl-0 = <0x4c>; pinctrl-names = "default"; power-domains = <0x1 0x20>; reg = <0x0 0xee0a0200 0x0 0x700>; - resets = <0x6 0x2be>; + resets = <0x6 0x2bf>; status = "okay"; }; Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-03-09ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPIMarek Vasut
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until we can do better using the new SPI NOR framework. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-03armv8: fsl-layerscape: avoid DT fixup warningLaurentiu Tudor
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node from the device tree. This causes this warning to be issued when doing the device tree fixup: WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND. Fix it by excluding the device tree fixup for the JR reserved by sec_firmware. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03armv8: fsl-layerscape: fix SEC QI ICID setupLaurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03configs: fsl: move DDR specific defines to KconfigRajesh Bhagat
Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- SoCFPGA cache/gpio fixes
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- Various Bananapi fixes
2019-02-28ARM: cache: Fix incorrect bitwise operationMarek Vasut
The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25ARM: rmobile: Imply SoC per boardMarek Vasut
Imply all SoCs supported by a given board. This allows building single U-Boot binary for boards which can have multiple SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: rmobile: Imply pinctrl drivers per SoCMarek Vasut
Imply preferred pin control driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: rmobile: Imply clock drivers per SoCMarek Vasut
Imply preferred clock driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: socfpga: Clear PL310 early in SPLMarek Vasut
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25ARM: socfpga: Configure PL310 latenciesMarek Vasut
Configure the PL310 tag and data latency registers, which slightly improves performance and aligns the behavior with Linux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25ARM: cache: Fix incorrect bitwise operationMarek Vasut
The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
2019-02-20Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2019-02-20Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
- Support of NXP's LX2160RDB and LX2160QDS platform - Enable SATA DM model for NXP's ARM SoCs
2019-02-20ARM: tegra: enable ums on nyan boardsTristan Bastian
This patch enables UMS on the nyan devices like the nyan-big. A patch like this has been sent in by Stephen Warren some time ago for other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec. But the nyan devices never received that functionality. Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20nyan-big: change spi delayTristan Bastian
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button. With this patch keyboard is working by only pressing [power] button. Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-19ARM: omap3: evm: Update DM SPL supportDerald D. Woods
- Switch to using the omap3-u-boot.dtsi file for needed properties - Enable SPL_OF_CONTROL This commit is based on the following series: https://patchwork.ozlabs.org/project/uboot/list/?series=92472 https://patchwork.ozlabs.org/project/uboot/list/?series=92462 Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-19omap3_beagle: Update for DM SPL supportTom Rini
- Switch to using the omap3-u-boot.dtsi file for needed properties. - Remove a few SPL features to free up more SRAM space. - Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to worry about X-Loader at this point anymore. - A few related updates to SPL options as part of switching to DM SPL. Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19ARM: omap3_logic: Enable SPL booting device treeAdam Ford
With the generic omap3-u-boot.dtsi file available, this patch increased the memory of the various incarnations of the omap3_logic board, and points their respective u-boot.dtsi files to the newly created generic one, and removes the PLATDATA from the board file. These are all done at once because the're all utilizing the same omap3logic.c board file. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-19ARM: DTS: omap3-u-boot.dtsiAdam Ford
Create generic omap3-u-boot.dtsi file that omap3 based boards can include to generate device tree in SPL for booting MLO. Credit should go to Tom Rini. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19board/BuR/brxre1: convert do DMHannes Schmelzer
This commit converts the brxre1 board to DM, for this we have todo following things: - add a devicetree-file for this board - drop all obsolete settings from board header-file - use dm_i2c_xxx calls for read/write to the resetcontroller - request gpios before operate them Serues-cc: trini@konsulko.com Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-19armv8: ls1043a: move SCSI_AHCI and SCSI to arm/KconfigPeng Ma
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface support. this changed is to fixed the ls1043ardb compile warning as fallows: ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal.See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> [PK: reword the patch subject] Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move CONFIG_LAYERSCAPE to KconfigRajesh Bhagat
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move TZASC and TZPC configs to KconfigRajesh Bhagat
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig for LS1088A and LS2088A platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19lx2160aqds : Add support for LX2160AQDS platformPankaj Bansal
LX2160AQDS is a development board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [PK: Sqaush patch for "secure boot defconfig" & add maintainer] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: emc2305: add support for fan controllerMeenakshi Aggarwal
Add support for fan controller emc2305. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160ardb : Add support for LX2160ARDB platformPriyanka Jain
LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: fsl-layerscape: reorder rgmii dpmacs' enablementPankaj Bansal
some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8, lx2160a: Initialize ethernet array in serdes_initPriyanka Jain
Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19arch: arm: lib: Flush L3 after relocation to DDRMeenakshi Aggarwal
Flush L3 cache after uboot relocated to DDR. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASEPriyanka Jain
As per hardware documentation, CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-18arm: socfpga: gen5: remove hacked ETH RST handlingSimon Goldschmidt
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon. This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18sunxi: Add Bananapi M2+ H5 boardChen-Yu Tsai
As the H5 is pin compatible with the H3, vendors tend to upgrade their existing H3 products with an H5 SoC swap. This is the case with the Bananapi M2+ H5. Add the following to support it: - device tree file: synced from Linux v5.0-rc1, - defconfig: copy of bananapi_m2_plus_h3_defconfig with only SoC family and default device tree file name changed - MAINTAINERS entry Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-18sunxi: Sync Bananapi M2+ device tree from Linux v5.0-rc1Chen-Yu Tsai
As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the device tree for the Bananapi M2+ has been split into a common dtsi file, and an SoC-specific board device tree file that includes both the shared dtsi file and the soc dtsi file. This was done to support both the H3 and H5 variants of the same board. This is similar to what was done for the Libre Computer ALL-H3-CC in U-boot commit d7b17f1c24af ("sunxi: Split out common board design for ALL-H3-CC device tree"). The newly split files are directly synced from Linux tag v5.0-rc1. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-16Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imxTom Rini
u-boot-imx-2019-02-16 --------------------- - vhybrid: add calibration - gw_ventana: fixes - Improve documentation for Secure Boot (HABv4) - Fix Marvell Switch - MX6 Sabre, switch to DM - Fixes for NAND
2019-02-15imx: cpu.c: give access to reset cause in splMax Krummenacher
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR register content intact so that U-Boot proper can evaluated the reset_cause again should this be needed. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warningsMarcel Ziswiler
This fixes the following warnings: arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/ #size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]Abel Vesa
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones from kernel v4.20 (commit 8fe28cb58bcb2). Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] filesAbel Vesa
This allows us to keep the basic dts[i] files up-to-date with the ones in kernel, but at the same time allowing the u-boot to add its own properties to the existing nodes. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGEAbel Vesa
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL, makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE. Everything that is not part of the usb storage support in SPL is now build under SPL_USB_HOST_SUPPORT. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15arm64: zynqmp: Change the spi-rx-bus-width property to x1Venkatesh Yadav Abbarapu
As per the zc1275 design x1 mode is enabled so changing the spi-rx-bus-width property to x1. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15arm64: zynqmp: Fix i2c boot warningShubhrajyoti Datta
Fix the below warning as the core looks for the compatible string. [ 5.198919] i2c i2c-18: of_i2c: modalias failure on /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19 [ 5.207454] i2c i2c-18: Failed to create I2C device for /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19 [ 5.216394] i2c i2c-18: of_i2c: modalias failure on /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30 [ 5.224986] i2c i2c-18: Failed to create I2C device for /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30 [ 5.233927] i2c i2c-18: of_i2c: modalias failure on /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35 [ 5.242527] i2c i2c-18: Failed to create I2C device for /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35 [ 5.263880] i2c i2c-18: of_i2c: modalias failure on /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36 [ 5.272477] i2c i2c-18: Failed to create I2C device for /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36 [ 5.281415] i2c i2c-18: of_i2c: modalias failure on /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51 [ 5.290008] i2c i2c-18: Failed to create I2C device for /amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51 Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15arm64: zynqmp: Remove autodetected devices without descriptionMichal Simek
It will never reach mainline that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15arm64: dts: Fix various entry-method properties to reflect documentationAmit Kucheria
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". Linux commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Linux docs: Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15xilinx: dts: Remove additional empty linesMichal Simek
Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15arm64: zynqmp: Add reset-on-timeout for all boards and modify default ↵Mounika Grace Akula
timeout value This patch adds reset-on-timeout to FPD WDT which will trigger an interrupt to PMU when watchdog expiry happens and PMU takes the necessary action. If this property is not enabled, reason will not be known when watchdog expiry happens. This patch also modifies the default timeout to 60 seconds. Reason is that if u-boot enables WDT, it will set the timeout to 10 seconds and this is not enough to boot till Linux and start the WDT application in Linux. 60 seconds is the maximum safest value to boot till Linux and start the WDT application. Users need to change this timeout value to fit their needs. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15ARM: dts: zynq: correct and improve the model property of dt filesLuis Araneda
Replace the current value of the model property by a more accurate description of each board (which includes the manufacturer), as some of the boards had the same value ("Xilinx Zynq") Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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