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2012-10-15i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfieldsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15i.MX6: Add ANATOP_PFD_480 bitfield constantsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15i.MX6: define IOMUX_GPR3 register bitfieldsEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15i.MX6: define bitfields for CHSCCDR registerEric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15i.MX6: change register name for CCM_CHSCCDR to match ref. manualEric Nelson
Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in reference manual, but was named chscdr in struct mxc_ccm_reg. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson
Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15pxa: Add code to examine cpu model and revisionLukasz Dalek
Add function which return CPU model and revision which can be used for cpu detection. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
2012-10-15tegra: nand: add board pinmuxLucas Stach
Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra: clean up board include hellLucas Stach
The prototypes used in board files were all scattered out, which lead to code duplication between SPL and normal U-Boot and some prototypes not actually being used. Consolidate this in a common board header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra: add funcmux entry for NAND attached to KBCLucas Stach
Secondary config for the Flash attachment. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra20: rework UART GPIO handlingLucas Stach
Rename board provided gpio_config_uart() to gpio_early_init_uart() as it does the same thing as the equally called function provided by the uart-switch code. This allows to simply call this function in early board init whether or not we are building with CONFIG_UART_SWITCH defined. Also provide a weak symbol for this function, to avoid the need to provide this function for boards that don't need any fixup. This patch supersedes the earlier posted "tegra: convert gpio_config_uart to weak symbol". Build tested with MAKEALL -s tegra20 Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra20: add clock_set_pllout functionLucas Stach
Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra20: complete periph_id enumLucas Stach
Most Tegra boards output the ULPI reference clock on pad DEV2. Complete the periph_id enum so that we are able to enable this clock output circuit. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15Tegra20: Move some code files to common directories for upcoming Tegra30 ↵Tom Warren
patches. Move files that are going to be common between T20 and T30 into 'tegra-common' subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs and modified for that SoC. The 'common' files should need only minor changes. Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a follow-on patch. Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15tegra20: add USB ULPI init codeLucas Stach
This adds the required code to set up a ULPI USB port. It is mostly a port of the Linux ULPI setup code with some tweaks added for more correctness, discovered along the way of debugging this. To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT have to be set in the board configuration file. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-10-15tegra20: port to new ehci interfaceLucas Stach
EHCI interface now supports more than one controller. Wire up our usb functions to use this new interface. Signed-off-by: Lucas Stach <dev@lynxeye.de>
2012-10-15usb: ehci: rework to take advantage of new lowlevel interfaceLucas Stach
Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15usb: lowlevel interface change to support multiple controllersLucas Stach
Carry an index in the lowlevel usb functions to make specify the respective usb controller. Also pass through an controller struct from lowlevel_init to the creation of the root usb device of this controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15serial: Remove CONFIG_SERIAL_MULTI from remaining sourcesMarek Vasut
Remove the parts depending either on disabled CONFIG_SERIAL_MULTI or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI is now enabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
2012-10-15serial: mxs: spl: Remove empty serial_* functions from SPL codeMarek Vasut
Remove the empty bodies from serial_* functions from MXS SPL code. These empty implementations are now in common/serial.c instead so declaring them also in the SPL code would cause a colision once serial multi is enabled unconditionally. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Stefano Babic <sbabic@denx.de>
2012-10-15ARM: prevent misaligned array initsAlbert ARIBAUD
Under option -munaligned-access, gcc can perform local char or 16-bit array initializations using misaligned native accesses which will throw a data abort exception. Fix files where these array initializations were unneeded, and for files known to contain such initializations, enforce gcc option -mno-unaligned-access. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Switch to usign call cc-option for -mno-unaligned-access as Albert had done previously as that's really correct] Signed-off-by: Tom Rini <trini@ti.com>
2012-10-08arm: armv7: omap3: Fix restore sequence in lowlevel_initAlbert ARIBAUD
The restore sequence in lowlevel_init was in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that of s_init, so move the s_init call after the restore and turn it into a tail-optimized branch. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2012-10-08arm: rmobile: bugfix: wrong register saving in lowlevel_initTetsuyuki Kobayashi
lowlevel_init() of rmobile badly assumed that ip register holds return address. The commit "63ee53a7 armv7 cpu_init_crit: Simplify code" breaks this assumption. This patch removes this bad assumption and simplify code. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2012-10-05arm: armv7: temporarily set -mno-unaligned-accessAlbert ARIBAUD
This patch aims at ensuring that the 2012.10 release works out-of-the-box on as many targets as possible, by reinstating commit 5347560f5427bcdd48a563b62180481606ac8044, which adds option -mno-unaligned-access to armv7 builds. This patch will be overriden immediately after release of 2012.10.
2012-10-04ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04arm: Support new Xilinx Zynq platformMichal Simek
Add timer driver. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2012-10-04arm: Fixed the offset for the no relocation.Zhong Hongbo
When the u-boot address of destination equal to __start, no relocation. relocation offset(r9) = 0. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Tested-by: Stefano Babic <sbabic@denx.de>
2012-10-04arm: Add CONFIG_OF_BOARD_SETUP support to bootmJoe Hershberger
ARM boards need to change device tree settings as well Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-10-04arm: Remove additional config flagsMichal Simek
These options are just duplicated from arch/arm/cpu/armv7/config.mk Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-10-04armv7 cpu_init_crit: Simplify codeBenoît Thébaudeau
We don't need to return to cpu_init_crit after calling lowlevel_init, so lowlevel_init can directly return to the caller of cpu_init_crit. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2012-10-04arm: work around assembler bugAllen Martin
Disable sibling call optimization based on binutils version. This is to work around a bug in the assember in binutils versions < 2.22. Branches to weak symbols can be incorrectly optimized in thumb mode to a short branch (b.n instruction) that won't reach when the symbol gets preempted. http://sourceware.org/bugzilla/show_bug.cgi?id=12532 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Tom Rini <trini@ti.com>
2012-10-04ARM: increase lmb stack space reservation to 4KBRob Herring
The bootm initrd image copy to ram can collide with the stack in cases where the print buffer size is large (i.e. 1K). The result is intermittent initrd decompression errors depending on the initrd size MOD 4KB since the initrd start address is 4KB aligned. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-10-03Merge remote-tracking branch 'u-boot-marvell/master'Albert ARIBAUD
2012-10-03ARM: kirkwood/orion5x: Use reset_cpu definition in include/common.hDinh Nguyen
include/common.h has the reset_cpu defined already. No need to re-define here. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03kirkwood: implement kw_sdram_size_adjustGerlando Falauto
Size of the SDRAM chips might differ between any two (otherwise identical) instances of the same board. So add a function kw_sdram_size_adjust() which reads out the current ram size for a given bank, and adjusts the Kirkwood's SDRAM window size register accordingly. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2012-10-03kirkwood: implement kw_sdram_bs_set()Gerlando Falauto
Some boards might be equipped with different SDRAM configurations. When that is the case, CPU CS Window Size Register (CS[0]n Size) should be set to the biggest value through board.cfg file; then its value can be fixed at runtime according to the detected SDRAM size. Therefore, implement kw_sdram_bs_set(). Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Marek Vasut <marex@denx.de> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03kirkwood: use c-struct for access to SDRAM addr decode registersHolger Brunck
Remove the defines and do this with a C-struct. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Marek Vasut <marex@denx.de> Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03kirkwood: fix mpp.h coding styleLuka Perkov
Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
2012-10-03ARM : Add GPIO Driver and IOMUX definition for S3C2440Gabriel Huau
It's now possible to use the gpio driver interface for s3c2440. This patch add iomux definitions too. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
2012-10-03rmobile: Fix build timer driver with BUILD_DIRNobuhiro Iwamatsu
Rmobile common timer driver diverts the same driver as SH architecture. When it builds at the same place with source, it is no problem, but when it builds out of source, it cannot build. This patch revises this problem. Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2012-10-03arm: rmobile: Add cpu_eth_init functionNobuhiro Iwamatsu
This supports ethernet driver of RMOBILE R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA boardHideyuki Sano
The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM, Ethernet, and more. This patch supports the following functions: - 512MB DDR3-SDRAM - Serial console (SCIF) - Ethernet MAC(MII) & PHY(SMSC) Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: Add support PFC of Renesas R8A7740Nobuhiro Iwamatsu
Renesas R8A7740 has GPIO based PFC. This privode framework of PFC. The code included in this base from linux kernel. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: Add support Renesas R8A7740Nobuhiro Iwamatsu
Renesas R8A7740 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: Add support TMU base timer functionNobuhiro Iwamatsu
Some rmobile SoC has TMU base timer function. This supports TMU. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: Change initializing ICCICR registerNobuhiro Iwamatsu
There is rmobile without ICCICR. ICCICR is initialized only when ICCICR is defined. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: kzm9g: separate cpu_rev to integer and fractionTetsuyuki Kobayashi
According to SoC document, revision info is separated to integer part and fracton part. So I separete rmobile_get_cpu_rev() to rmobile_get_cpu_rev_integer() and rmobile_get_cpu_rev_fraction(). Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03arm: rmobile: kzm9g: fix CPU infoTetsuyuki Kobayashi
CPU info register was read wrongly by mistake. And function rmobile_get_cpu_rev() was not called properly. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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