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2018-08-13ARM: socfpga: clk: Convert to clock frameworkMarek Vasut
Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodesMarek Vasut
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut
The variables removed in this patch are never used, they are only ever assigned and then waste precious memory. Drop both the assignment and the variables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut
The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut
Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut
Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Zap unused reset codeMarek Vasut
Remove code from the reset manager that is never called. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Zap all the UART handling complexityMarek Vasut
The UART reset handling is now done via reset framework using the SoCFPGA reset driver. The UART console assignment is done using the DM and console framework. Nuke all this comlexity, since it is just duplicating the same functionality, badly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13ARM: socfpga: Enable DM I2C framework on A10Marek Vasut
Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Enable DM reset framework on A10Marek Vasut
Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Add i2c alias to A10 SoCDKMarek Vasut
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign the I2C bus a bus number. Add the missing alias. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Add missing I2C resetsMarek Vasut
The I2Cx resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Fix Arria10 GMAC resetsMarek Vasut
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs to work and add GMAC2 reset and OCP resets which were missing altogether. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Add missing UART resetsMarek Vasut
The UART0 and UART1 resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: dts: socfpga: Flag reset manager on A10 as pre-relocMarek Vasut
The Altera reset manager block must be available very early on, since it controls ie. UART resets. Flag it as pre-reloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Register the FPGA on A10 in SPL againMarek Vasut
The restructuring of the SPL dropped registration of the FPGA in SPL, readd it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Fixes: c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
2018-08-13arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt
Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: fix device trees to work with DM serialSimon Goldschmidt
Device trees need to have the serial console device available before relocation and require a stdout-path in chosen at least for SPL to have a console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: cyclone5: handle debug uartSimon Goldschmidt
If CONFIG_DEBUG_UART is enabled, correctly initialize the debug uart before console is initialized to debug early boot problems in SPL. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: spl_gen5: clean up malloc_base assignmentSimon Goldschmidt
In spl_gen5's board_init_f(), gd->malloc_base is manually assigned at the end of the function to point to sdram. This code is outdated as by now, the heap is switched to sdram by the common function spl_relocate_stack_gd() if the appropriate defines are set. As it was, the value assigned manually was directly overwritten by this common code, so remove the manual assignment. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13arm: socfpga: fix SPL on gen5 after moving to DM serialSimon Goldschmidt
There were NULL pointers dereferenced because DM was used too early without correct initialization: - malloc_simple returned NULL when called from preloader_console_init() because gd->malloc_limit was 0 - uclass_add dereferenced gd->uclass_root members which were NULL because dm_init (or one of its relatives) has not been called. All this is fixed by calling spl_early_init before calling preloader_console_init. This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-10snapdragon: Add DRAM detection & FDT fixupRamon Fried
Fixup the Linux FDT with the detection of onboard DRAM as provided by SBL (Secondary boot loader) by reading the shared-memory region. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-10stm32mp1: add gpio led supportPatrick Delaunay
This patch add the 4 LED available on the ED1 board and activated gpio led driver. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-08-10Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2018-08-08usb: rockchip: implement K_FW_LBA_ERASE_10 commandAlberto Panizzo
This command is part of the write partition sequence performed by rkdeveloptool: one partition is first completely erased and than wrote. Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08usb: rockchip: implement K_FW_LBA_READ_10 commandAlberto Panizzo
This patch implement reading blocks form selected device with LBA addressing. Corresponding command on workstation is: rkdeveloptool rl <start_blk> <blk_cnt> <file> While we support reading more than one blocks per K_FW_LBA_READ_10 request, rkdeveloptool and original rockchip tool do perform chunk reads limiting the maximum size per chunk far lower than max int values. Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-07Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini
2018-08-07Merge tag 'xilinx-for-v2018.09-rc2' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx fixes for v2018.09-rc2 xilinx: - Add support for zybo z7 and ultra96 - Tune zynq and zynqmp mini configurations - Move SYS_MALLOC_LEN to Kconfig fdt - make static funcs gpio: - Fix soft gpio driver - Fix Zynq gpio driver by using platdata microblaze: - Fix Kconfig entry spi - Move ISSI to Kconfig
2018-08-07arm: zynq: dts: add spi flash node to zedboardLuis Araneda
Add a flash node to fix the detection of the memory IC. With the changes introduced with commit 8fee8845e754 ("enf_sf: reuse setup_flash_device instead of open coding it") the SPI speed is now read from device-tree or a default value is applied. This replaced the old behavior of setting the SPI speed to CONFIG_ENV_SPI_MAX_HZ. As this board didn't have a flash node, the default value was applied to the SPI speed, producing an error when probing the flash memory (speed too slow). Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-07ARM: kirkwood: add SBx81LIFXCAT boardChris Packham
This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GP24 and SBx81GT24 cards cards collectively referred to as SBx81LIFXCAT in u-boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07arm: mvebu: clearfog: add u-boot, dm-spl tag for spiJon Nettleton
This is required so SPL and u-boot can boot from spi flash devices that use the dm drivers. Signed-off-by: Jon Nettleton <jon@solid-run.com> [baruch: use -u-boot.dtsi] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07arm: mvebu: helios4: remove duplicate sdhci pins nodeBaruch Siach
The same pinctrl node appears in the solidrun-microsom dtsi. Use that instead. Cc: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Dennis Gilmore <dennis@ausil.us> Tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07arm: mvebu: Better align Clearfog dts file with Linux kernelJon Nettleton
This makes changes so the u-boot dts file is structured more similar to the mainline linux dtsi file. It provides a minimal common dts that can work for most boards based on the ClearFog platform. Ethernet support is only supported for eth0 however all devices are left enabled so u-boot can generate and provide mac addresses for all of the network interfaces. Signed-off-by: Jon Nettleton <jon@solid-run.com> [baruch: rebase on recent changes] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Dennis Gilmore <dennis@ausil.us> Tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07arm: mvebu: clearfog: use the microsom .dtsiBaruch Siach
Use hardware description from the recently introduced microsom .dtsi file to reduce duplication. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Dennis Gilmore <dennis@ausil.us> Tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07arm: mvebu: solidrun-microsom: update SPI flash compatibleBaruch Siach
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: support UART boot imageBaruch Siach
The kwboot utility can use the generated image to boot mvebu SoCs from UART. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: select boot device at SoC levelBaruch Siach
Move the gdsys Controlcenter DC specific build time kwbimage.cfg generation code into the mach-mvebu/ directory to be shared by all 32bit mvebu platforms. Remove board specific kwbimage.cfg files, and use the generated one instead. These files are all identical, with two exceptions. Clearfog and Helios4 use the sdio boot device, whereas all others use spi. Update the defconfigs for the exceptional boards to generate the same kwbimage.cfg as before. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: consolidate SPL boot device config symbolsBaruch Siach
Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of board specific symbols. This commit enables the boot device selection menu to all mvebu platforms, but it is only effective on Turris Omnia and gdsys Controlcenter DC platforms. A following commit will enable boot selection for other platforms. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: a38x: drop duplicate platform id symbolsBaruch Siach
Use generic mvebu Kconfig symbols like all other mvebu boards. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06arm64: zynqmp: Add support for Avnet Ultra96Michal Simek
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files and point to origin internal board name. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: add support for the zybo z7 boardLuis Araneda
The board is manufactured by Digilent Main features: - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20) - RAM: 1 GB DDR3L - FLASH: 16 MB QSPI - 1 Gbps Ethernet - USB 2.0 - microSD slot - Pcam camera connector - HDMI Tx and Rx - Audio codec: stereo out, stereo in, mic - 5 (Z7-10) or 6 (Z7-20) Pmod ports - 6 push-buttons, 4 switches, 5 LEDs - 1 (Z7-10) or 2 (Z7-20) RGB LEDs Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynqSiva Durga Prasad Paladugu
This patch moves the the config SYS_MALLOC_LEN to Kconfig. It will be just for Zynq arch and to do will be for all other archs. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: Fix indentation for zynq-cse targetsMichal Simek
Trivial DT style fixes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: Remove fclk-enable property for cse-nor targetMichal Simek
Mini cse NOR configuration is running without PL that's why there is no reason to enable clock to PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynqmp: Fix sdhci clock in emmc1 mini configurationMichal Simek
Add missing clocks property with fix clock-names property to be aligned with emmc0 configuration and binding doc. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: spring: fix alias of mmc correctlyMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06arm: exynos5: fix warning of dtsMinkyu Kang
remove this warning: avoid_unnecessary_addr_size Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06arm: exynos4: fix warning of dtsMinkyu Kang
remove this warning: avoid_unnecessary_addr_size Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-04Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-08-03ARM: dts: stm32: remove cd-inverted for stm32429i-evalPatrice Chotard
As cd-inverted property is no more used by arm_pl180_mmci driver, remove it. Update cd-gpios active level accordingly. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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