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2015-04-01ARM: atmel: at91sam9x5ek: enable spl supportBo Shen
Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-04-01ARM: atmel: at91sam9m10g45ek: enable spl supportBo Shen
Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-04-01ARM: atmel: arm926ejs: fix clock configurationBo Shen
Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed. Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Heiko Schocher <hs@denx.de>
2015-04-01spl_atmel.c: Switch s_init to board_init_fTom Rini
To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an empty stub of s_init(). It can be removed when lowlevel_init becomes s_init. Cc: Bo Shen <voice.shen@atmel.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini@ti.com> [rebased on current master, leave s_init() as empty stub] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-04-01ARM: atmel: armv7: switch to use common timer functionsBo Shen
The commit 8dfafdd (Introduce common timer functions), add common timer functions, we can use them directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-04-01ARM: atmel: arm9: switch to use common timer functionsBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-03-29sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clockIain Paton
make the CPU clock selectable via Kconfig this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each soc header and replaces it's use in board/sunxi/board.c with CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board specific frequency on boot Signed-off-by: Iain Paton <ipaton0@gmail.com> [hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the arch-timer clk speed on sun7i to fix mis-compile on sun7i] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-03-29sunxi: sun4i: improve cpu clock selection methodIain Paton
clock_set_pll1 would pick the next highest available cpu clock speed if a value not in the pre defined table was selected. this potentially results in overclocking the soc. reverse the selection method so that we select the next lowest speed and add the missing 912Mhz setting that's requested by sun7i which also uses the sun4i clock code. Signed-off-by: Iain Paton <ipaton0@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-03-29sunxi: musb: Fix some lo speed devices not working with musb hostHans de Goede
The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a high speed squelch on usb reset deassert when a lo speed device is plugged in. The android kernel has a work around for this in the form of temporary disabling the phy's squelch detection on reset deassert, this commit adds the same workaround to the u-boot sunxi musb code, thereby fixing various usb lo speed devices not working. Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless keyboard/mouse combo receiver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-03-28armv8: semihosting: delete external interfaceLinus Walleij
Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28armv8: semihosting: add a command to load semihosted imagesLinus Walleij
Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28armv8: semihosting: do not inline trap callLinus Walleij
The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28ARM: bcm283x: move SoC headers to mach-bcm283x/include/machMasahiro Yamada
Move arch/arm/include/asm/arch-bcm283x/* -> arch/arm/mach-bcm283x/include/mach/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-03-28ARM: bcm283x: merge BCM2835/BCM2836 directories into mach-bcm283xMasahiro Yamada
BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2) are similar enough. One of the biggest differences is the ARM processor. It is reasonable to collect the source files into a single place, arch/arm/mach-bcm283x/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-03-28malloc_f: enable SYS_MALLOC_F by default if DM is onMasahiro Yamada
This option has a bool type, not hex. Fix it and enable it if CONFIG_DM is on because Driver Model always requires malloc memory. Devices are scanned twice, before/after relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc memory before relocation. As it is board-independent, handle it globally. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LENMasahiro Yamada
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig as 0x400. Each defconfig or Kconfig need not repeat the same value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28generic-board: move __HAVE_ARCH_GENERIC_BOARD to KconfigMasahiro Yamada
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-24remove unnecessary version.h includesRob Herring
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2015-03-24ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada
The callee (arch/arm/lib/cache-cp15.c) has a #ifdef CONFIG_SYS_DCACHE_OFF conditional. The same conditional in the caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot properMasahiro Yamada
The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: optimize kicking secondary CPUs codeMasahiro Yamada
Currently, the secondary CPU(s) are kicked three times: Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux. It makes the boot sequence very complicated. This commit merges the first and the second kicks, so the secondary CPU(s) can directly jump from SPL to Linux. arch/arm/mach-uniphier/smp.S is no longer necessary. Linux boot test passed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: fix typos in commentsMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: add empty lowlevel_init to U-boot properMasahiro Yamada
To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: use CONFIG_SPL_STACK to define SPL stack pointerMasahiro Yamada
Ifdef conditionals for CONFIG options are not Kconfig-friendly. Instead, define CONFIG_SPL_STACK to prepare for Kconfig moves. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: enable Driver Model and UART on SPLMasahiro Yamada
Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide Driver Model UART support on SPL. CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple malloc is preferred on SPL. Dlmalloc requires some static variables on .data section that is not available yet for NOR boot mode etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: move UART pin settings to SPLMasahiro Yamada
The UniPhier platform is going to enable Driver Model and UART support on SPL. Move UART pin settings to early_pin_init(), which is called from SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: move platform devices to SPLMasahiro Yamada
Since we do not have OF_CONTROL support for SPL, platform devices are necessary to enable Driver Model on SPL. To prepare for that, move platdevice.o to SPL and enable it by CONFIG_SPL_DM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: include PH1-LD4 Makefile from PH1-sLD8Masahiro Yamada
The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile are completely the same. We can improve the maintainability by having one to include the other. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24ARM: UniPhier: remove unnecessary CONFIG_SYS_SOCMasahiro Yamada
Since commit a86ac9540e20 (ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>), UniPhier platform does not need the symbolic link arch/arm/include/asm. This option is not necessary either. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-20Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini
2015-03-18ARM: atmel: sama5d4: set non-secured for peripheralsBo Shen
When access the programmable secure peripherals address space, it needs set them to non-secured. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-03-18ARM: atmel: armv7: move spl lds to armv7 directoryBo Shen
As the u-boot-spl.lds is used only for armv7 SoCs (includes sama5d3 and sama5d4), so move it to armv7 directory. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-03-18ARM: at91: at91sam9rlek: add mci supportWu, Josh
This patch enable the MCI support for at91sam9rlek board. Signed-off-by: Josh Wu <josh.wu@atmel.com> [rebase on ToT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-03-18Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2015-03-15Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2015-03-15ARM: UniPhier: adjust device trees for business transferMasahiro Yamada
Panasonic's System LSI products, UniPhier SoC family, have been transferred to Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-13ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configurationNishanth Menon
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance. These apply to both OMAP5 and DRA7. Reported-by: Vivek Chengalvala <vchengalvala@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1Nishanth Menon
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced. As part of this change, move to using the generic lowlevel_init.S for omap3 as well. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCsNishanth Menon
This is in preperation of using generic cross OMAP code. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: OMAP: Change set_pl310_ctrl_reg to be genericNishanth Menon
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: Introduce erratum workaround for 621766Nishanth Menon
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: Introduce erratum workaround for 430973Nishanth Menon
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: Introduce erratum workaround for 454179Nishanth Menon
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13ARM: Introduce erratum workaround for 798870Nishanth Menon
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13mx6: soc: Switch to cold resetDirk Behme
Disable the warm reset and enable the cold reset for a more reliable restart ('reset'). This is taken from the Linux kernel, see imx_src_init() in arch/arm/mach-imx/src.c. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
2015-03-13imx:mx6 remove duplicated includesPeng Fan
There is no need to include asm/bootm.h twice, so remove one. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-03-10Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>