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2016-02-18ARM: at91: sama5d2: configure the L2 cache memorySamuel Mescoff
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18arm: at91: Add support for DENX MA5D4 SoM and EVKMarek Vasut
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clean up the PMC_PLLICPR init codeWenyou Yang
Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add PMC_PLLICPR init functionWenyou Yang
To avoid the duplicated code, add the PMC_PLLICPR init function. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add PLLB enable/disable functionsWenyou Yang
To avoid the duplicated code, add the PLLB handle functions. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de> [add enable/disable functions to arm920t] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: armv7: clean up UTMI PLL handle codeWenyou Yang
Due to introducing the UTMI PLL enable function, use this function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add UTMI PLL enable/disable functionWenyou Yang
To avoid the duplicated code, add the UTMI PLL handle functions, and add PMC_USB init function too. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: cpu: at91: clean up peripheral clock codeWenyou Yang
Due to introducing the new peripheral clock handle functions, use these functions to clean up the duplicated code. Meanwhile, remove unneeded header file include, at91_pmc.h. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixup for arm920t code] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add a new file to handle clockWenyou Yang
To reduce the duplicated code, add a new file to accommodate the peripheral's and system's clock handle code, shared with the SoCs with different ARM core. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: asm/at91_pmc.h: fix trival register offsetWenyou Yang
Remove unnecessary #ifdef CPU_HAS_PCR. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-15arm: build some file(s) as ARM mode onlyDavid Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15arm: the ARM920T is THUMB capable, so select the appropriate ISADavid Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)David Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-14Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-02-14ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boardsMasahiro Yamada
Initial commit for PH1-Pro4 Ace and Sanji boards. Note: There are two variants for the Ace board in terms of the amount of DDR memory; 1GB or 2GB. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil boardMasahiro Yamada
This is used for on-board inter-connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil boardMasahiro Yamada
This board has an EEPROM connected to the I2C channel 0 of the SoC. Its slave address is 0x54. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: adjust DDR clock delay line for ProXstream2Masahiro Yamada
It turned out that DDR channel 2 was not working on ProXstream2 Vodka board. Add the missing ACBLDR0 register setting to adjust the delay between the clock lines and the address/command lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: move cmd_ddrmphy.c to fix build errorMasahiro Yamada
If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada
The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: remove unused header mio-regs.hMasahiro Yamada
This header is no longer used. This is the last file in arch/arm/mach-uniphier/include/mach/. At last, I've succeeded in eliminating the mach directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: drop unneeded EHCI pin mux settingsMasahiro Yamada
These pin mux settings are cared by the pinctrl drivers. Remove the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: switch over to generic EHCI driverMasahiro Yamada
The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does nothing special but set the base address and handle reset/clock. Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"), the generic one (drivers/usb/host/ehci-generic.c) can do those, too. We no longer need to stick to the dedicated driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add clocks properties to EHCI nodesMasahiro Yamada
This allows the EHCI driver to get clocks from device tree. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add device nodes for MIO control blockMasahiro Yamada
This block provides clock and reset control for MIO (Media I/O) hardware blocks such as USB2.0, SD card, eMMC, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add device nodes for Peripheral control blockMasahiro Yamada
This block provides clock and reset control for peripherals such as UART, I2C, IC card, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add device nodes for System Control blocksMasahiro Yamada
These are mainly used for controlling clocks and resets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: dts: uniphier: add reference clock nodesMasahiro Yamada
Add master clock nodes generated by crystal oscillators. PH1-sLD3, PH1-LD4: 24.576 MHz PH1-Pro4, ProXstream2: 25.000 MHz PH1-Pro5: 20.000 MHz Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada
This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoCMasahiro Yamada
The USB boot code is too fat and complicated to be included in SPL (at least for now). So, it was implemented as a separate project (what we call USB-loader). The expected boot sequence is as follows: Boot ROM -> USB-loader -> SPL -> U-Boot proper The USB-loader loads the SPL and U-Boot proper from a USB memory onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper to DRAM, so this mode looks like a NOR boot from the view of SPL. However, we want to distinguish between (genuine) NOR boot and USB boot in some places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: add missing static qualifierMasahiro Yamada
This function is for local use in the file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: create early page table at run-timeMasahiro Yamada
UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead, locked outer cache is used as RAM area during the early boot stage where DRAM is not ready yet. This effectively means MMU must be always enabled while we are in SPL. Currently, the SPL image for UniPhier SoCs contains the page table statically defined at compile time. It has been a burden because the 16KB page table occupies a quarter memory footprint of the 64KB SPL image. Finally, there is no more room to implement new features in SPL. Setting aside the NOR boot mode, this issue can be solved by creating the page table onto RAM at run time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: change stack pointer address for SPLMasahiro Yamada
No special reason for the current stack address 0x0ff08000. Change it to 0x00100000 to simplify the init_page_table. There are two types of SoCs in terms of the load address of SPL. [1] PH1-sLD3, PH1-LD4, PH1-sLD8 SPL is loaded at 0x00040000-0x0004ffff [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b SPL is loaded at 0x00100000-0x0010ffff The new stack area (0x000f8000-0x00100000) should be safe for all the cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14spl: define BOOT_DEVICE_USBMasahiro Yamada
This enum is referenced from common/spl/spl.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada
Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-12zynqmp: nand: Add Nand driver support for zynqmpSiva Durga Prasad Paladugu
Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [scottwood: Fix checkpatch warning] Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-11Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2016-02-11video: tegra: Enable the 'lcd' env variable work-aroundSimon Glass
Enable this option on all tegra boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2016-02-08ARM: dts: k2g: Add keystone net dts filesMugunthan V N
Add keystone net DT support for k2g evm. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-08OMAP3_LOGIC: Setup defconfig to enable SPL and NAND bootingAdam Ford
The defconfig patch will enable the the SPL and NAND settings. The update to Kconfig will allow the SPL to configured in and built. Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-08serial: serial_stm32: move clock config from driver to boardVikas Manocha
This patch removes the uart clock enable from serial driver & move it in the board code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-06Use correct spelling of "U-Boot"Bin Meng
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-04imx: mx6: implement mmc_get_env_devPeng Fan
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-02-04imx: mx7dsabresd: move mmc_get_env_devno to soc codePeng Fan
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to match the one in common/env_mmc.c. Introduce a weak function board_mmc_get_env_dev. Different boards can implement this according to sdhc controller which is used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-02-02arm: pcm052: Add device tree file'sBhuvanchandra DV
- Add device tree files for Phytec phyCORE-Vybrid Board. - Enable lpuart support for Phytec phyCORE-Vybrid Board. - Use UART1 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02arm: vf610-twr: Add device tree file'sBhuvanchandra DV
- Add device tree files for NXP/Freescale VF610 Tower Board. - Enable lpuart support on NXP/Freescale VF610 Tower Board. - Use UART1 as stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02arm: colibri-vf: Enable serial supportBhuvanchandra DV
- Enable lpuart support on Toradex Colibri VF50/VF61 - Use UART0 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02arm: vybrid: Update the license stringBhuvanchandra DV
Since SPDX license is already there, drop the full one. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02arm: vybrid: Enable lpuart supportBhuvanchandra DV
Add device tree node's for lpuart on Vybrid platform Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculationYe Li
The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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