uboot-2021-rebase.git - uboot 2021 rebase, to fix booting on modern SD cards, from https://github.com/fifteenhex/u-boot/tree/am335x_som

Age	Commit message (Collapse)	Author
2012-08-24	MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefiles	Daniel Schwierzeck
	Prepare for upcoming MIPS64 CPU support. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-08-24	MIPS: factor out endianess flag handling to arch config.mk	Daniel Schwierzeck
	This is CPU independent and should be configured architecture-wide. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-08-17	dm: mips: Fix lb60 timer code	Marek Vasut
	The timer code contains more halfword writes which trigger gcc errors. The registers are again 32bit, yet written by 16bit writes, fix this: timer.c: In function ‘reset_timer_masked’: timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘get_timer_masked’: timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘timer_init’: timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2012-08-17	dm: mips: Fix lb60 WDT control	Marek Vasut
	Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2011-10-10	MIPS: Ingenic XBurst Jz4740 processor support	Xiangfu Liu
	Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>