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This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
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As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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