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This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
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Add lowlevel ag102 soc support.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Add device address offsets header of ag102 soc.
Add ag102 into mach-types.h.
Add asm-offsets.c for helping convert C headers into asm.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Correct definition of vector table in start.S
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
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Add linkage support to watchdog.S.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Remove unneccessary codes.
1. Clean up for cpu related code.
2. Clean up for timer related code.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Make linker script handles .data.rel sections.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
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SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.
This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.
Start procedure:
start.S will start up the N1213 CPU core at first,
then jump to SoC dependent "lowlevel_init.S" and
"watchdog.S" to configure peripheral devices.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
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