summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc85xx/cmd_errata.c
AgeCommit message (Collapse)Author
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_LBC103Kumar Gala
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_DDR120Kumar Gala
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal
Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal
Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134York Sun
Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/85xx: Rename MPC8572 DDR erratum to DDR115York Sun
Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc85xx: Implement workaround for erratum DDR-A003York Sun
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)Kumar Gala
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala
CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala
CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang
False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang
Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-1485xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_INBecky Bruce
This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/p4080: Add workaround for erratum CPU22Kumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/p4080: Add workaround for errata SERDES8Kumar Gala
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16powerpc/85xx: Add command to report errata workaroundsKumar Gala
Add 'errata' command to report what errata we workaround. Report workaround for erratum SATA-A001 on P1022/P1013. Also sorted the CONFIG_CMD_* list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit (git 2.34.1) at 2025-01-06 15:14:34 +0000