summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc85xx/release.S
AgeCommit message (Collapse)Author
2017-10-23powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary coresYork Sun
Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907") clears L1CSR2 for the boot core, but other cores don't run through the workaround. Add similar code for secondary cores to clear DCSTASHID field in L1CSR2 register. Signed-off-by: York Sun <york.sun@nxp.com>
2015-03-24remove unnecessary version.h includesRob Herring
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2014-04-22PPC: 85xx: Remove IVOR resetAlexander Graf
There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-24Remove obsolete _LINUX_CONFIG_H macroMasahiro Yamada
Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-08-09powerpc/mpc85xx: Workaround for A-005812York Sun
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-24powerpc/chassis2: Change core numbering schemeYork Sun
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun
The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming
Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-12-05powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese
By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
2012-11-27powerpc/mpc85xx: Temporary fix for spin table backward compatibilityYork Sun
Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1York Sun
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Remove R6 from spin tableYork Sun
R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500York Sun
Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: fix Unicode characters in release.STimur Tabi
Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23powerpc/mpc8xxx: fix core id for multicore bootingYork Sun
For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23powerpc/fsl-corenet: work around erratum A004510Scott Wood
Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditionalYork Sun
This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-06powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040EYork Sun
Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06powerpc/mpc85xx: Workaround for erratum CPU_A011York Sun
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06powerpc/P4080: Check SVR for CPU22 workaroundYork Sun
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
2011-11-29powerpc/85xx: Add workaround for erratum CPU-A003999Kumar Gala
Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Handle the lack of L2 cache on P2040/P2040EKumar Gala
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated valueWolfgang Denk
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/p4080: Add workaround for erratum CPU22Kumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-21Move arch/ppc to arch/powerpcStefan Roese
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
generated by cgit (git 2.34.1) at 2024-12-25 03:12:10 +0000