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2013-03-18Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
2013-03-15Replace __bss_end__ with __bss_endSimon Glass
Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-12Refactor linker-generated arraysAlbert ARIBAUD
Refactor linker-generated array code so that symbols which were previously linker-generated are now compiler- generated. This causes relocation records of type R_ARM_ABS32 to become R_ARM_RELATIVE, which makes code which uses LGA able to run before relocation as well as after. Note: this affects more than ARM targets, as linker- lists span possibly all target architectures, notably PowerPC. Conflicts: arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds arch/arm/cpu/armv7/omap-common/u-boot-spl.lds board/ait/cam_enc_4xx/u-boot-spl.lds board/davinci/da8xxevm/u-boot-spl-da850evm.lds board/davinci/da8xxevm/u-boot-spl-hawk.lds board/vpac270/u-boot-spl.lds Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-02-07common/fdt_support.c: sparse fixesKim Phillips
trivial: fdt_support.c:89:64: warning: Using plain integer as NULL pointer fdt_support.c:325:65: warning: Using plain integer as NULL pointer fdt_support.c:352:65: warning: Using plain integer as NULL pointer For the following bad constant expression, We hardcode the max. number of memory banks to four for the foreseeable future, and add an error with instructions on what to do once it's exceeded: fdt_support.c:397:22: error: bad constant expression For the rest below, sparse found a couple of wrong endian conversions in of_bus_default_translate() and fdt_get_base_address(), but otherwise the rest is mostly annotation fixes: fdt_support.c:64:24: warning: cast to restricted __be32 fdt_support.c:192:21: warning: incorrect type in assignment (different base types) fdt_support.c:192:21: expected unsigned int [unsigned] [usertype] tmp fdt_support.c:192:21: got restricted __be32 [usertype] <noident> fdt_support.c:201:21: warning: incorrect type in assignment (different base types) fdt_support.c:201:21: expected unsigned int [unsigned] [addressable] [usertype] tmp fdt_support.c:201:21: got restricted __be32 [usertype] <noident> fdt_support.c:304:13: warning: incorrect type in assignment (different base types) fdt_support.c:304:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:304:13: got restricted __be32 [usertype] <noident> fdt_support.c:333:13: warning: incorrect type in assignment (different base types) fdt_support.c:333:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:333:13: got restricted __be32 [usertype] <noident> fdt_support.c:359:13: warning: incorrect type in assignment (different base types) fdt_support.c:359:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:359:13: got restricted __be32 [usertype] <noident> fdt_support.c:373:21: warning: cast to restricted __be32 fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types) fdt_support.c:963:48: expected restricted __be32 const [usertype] *p fdt_support.c:963:48: got unsigned int [usertype] *<noident> fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types) fdt_support.c:971:48: expected restricted __be32 const [usertype] *p fdt_support.c:971:48: got unsigned int [usertype] *<noident> fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types) fdt_support.c:984:29: expected restricted __be32 const [usertype] *cell fdt_support.c:984:29: got unsigned int [usertype] *addr fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types) fdt_support.c:996:32: expected restricted __be32 const [usertype] *cell fdt_support.c:996:32: got unsigned int [usertype] *addr fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types) fdt_support.c:1041:41: expected restricted __be32 const [usertype] *cell fdt_support.c:1041:41: got unsigned int [usertype] *addr fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types) fdt_support.c:1053:41: expected restricted __be32 const [usertype] *range fdt_support.c:1053:41: got unsigned int const [usertype] *[assigned] ranges fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types) fdt_support.c:1064:53: expected restricted __be32 const [usertype] *addr fdt_support.c:1064:53: got unsigned int [usertype] *addr fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types) fdt_support.c:1110:50: expected restricted __be32 const [usertype] *addr fdt_support.c:1110:50: got unsigned int *<noident> fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types) fdt_support.c:1121:49: expected restricted __be32 const [usertype] *cell fdt_support.c:1121:49: got unsigned int *<noident> fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types) fdt_support.c:1147:60: expected restricted __be32 const [usertype] *addr fdt_support.c:1147:60: got unsigned int *<noident> fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static? fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types) fdt_support.c: In function 'fdt_node_offset_by_compat_reg': fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default] See also linux kernel commit 0131d897 "of/address: use proper endianess in get_flags". Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-04ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass
This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move dp_alloc_base, dp_alloc_top to arch_global_dataSimon Glass
Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move used_tlb_cams to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move CONFIG_QE to arch_global_dataSimon Glass
Move the quantative easing fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_dataSimon Glass
Move these fields into arch_global_data and tidy up. This is needed for both ppc and m68k since they share the i2c driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass
Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01ppc: Move clock fields to arch_global_dataSimon Glass
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy up. Leave pci_clk on its own since this should really depend only on CONFIG_PCI and not any particular chip type. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01ppc: Move brg_clk to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-30powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu
When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg
If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood
e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha
The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha
Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal
- Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Reserve default boot pageYork Sun
The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-12-13env: Use getenv_yesno() more generallyJoe Hershberger
Move the getenv_yesno() to env_common.c and change most checks for 'y' or 'n' to use this helper. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-12-05powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese
By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
2012-11-27powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLEYork Sun
Fix a bug introduced by this patch powerpc/mpc85xx: Temporary fix for spin table backward compatibility Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in cpu_init.c. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27powerpc/85xx: update the work-around for P4080 erratum SERDES-9Timur Tabi
The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27powerpc/p4080ds: fix PCI-e x8 link training down failureYuanquan Chen
Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27powerpc/85xx: implement check for erratum A-004580 work-aroundTimur Tabi
The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27powerpc/mpc85xx: Temporary fix for spin table backward compatibilityYork Sun
Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27powerpc/85xx: implement check for erratum A-004849 work-aroundTimur Tabi
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a deadlock under certain traffic patterns causing the system to hang") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004849, we can do this by verifying that the values in the specific registers that the work-around says to update. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-278xxx: Change all 8*xx_DDR addresses to 8xxxAndy Fleming
There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-26spl/85xx: new SPL supportScott Wood
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone. CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-11-26spl/powerpc: introduce CONFIG_SPL_INIT_MINIMALScott Wood
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific. Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: factor out START, and change cpu_init_nand.c to spl_minimal.c Cc: Andy Fleming <afleming@freescale.com>
2012-11-26powerpc/mpc85xx: consistently use COBJS-yScott Wood
A subsequent patch will conditionalize some of the files that are currently unconditional. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-11-26spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.cScott Wood
There is nothing really NAND-specific about this file. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-11-26spl/mpc85xx: move udelay to cpu codeScott Wood
It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-11-26powerpc/mpc85xx: fix TLB alignmentScott Wood
In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood <scottwood@frescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-11-26powerpc/mpc85xx: add comma before "already enabled"Scott Wood
Now outputs like this: L2: 512 KB already enabled, moving to 0xf8f80000 rather than this: L2: 512 KB already enabledmoving to 0xf8f80000 Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@gmail.com>
2012-11-26powerpc/mpc85xx: move debug tlb entry after TLB is in known stateScott Wood
Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Andy Fleming <afleming@freescale.com> -- Prabhakar, please test that debug still works.
2012-11-04powerpc/mpc85xx: sparse fixesKim Phillips
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04arch/powerpc/lib/board.c, *traps.c: sparse fixesKim Phillips
traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static? traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static? board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static? board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static? board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static? board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static? board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static? board.c:405:53: warning: Using plain integer as NULL pointer Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-22Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini
2012-10-2285xx: Protect timeout_save variable with ifdefsAndy Fleming
The timeout_save variable was only used by the DDR111_134 erratum code. It was being set, but never used. Newer compilers will actually complain about this. Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/boot: Change the compile macro for SRIO & PCIE boot master moduleLiu Gang
Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22poweprc/85xx: add QMan frequency info and fdt fixup.Haiying Wang
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22mpc85xx/portals: Add qman and bman ip_cfg field into portal infoHaiying Wang
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the total portal number, buffer pool number etc, we can use this info to limit those resources in kernel driver. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platformYork Sun
New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1York Sun
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Remove R6 from spin tableYork Sun
R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Add workaround for DDR erratum A004934York Sun
After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: software workaround for DDR erratum A-004468York Sun
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc8xxx: Fix DDR initialization waiting for D_INITYork Sun
When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit (git 2.34.1) at 2024-12-27 16:08:30 +0000