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path: root/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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2011-04-04powerpc/8xxx: Fix typo for address hashing messageKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-24powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-10powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun
When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-24powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala
ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-198xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20Disable unused chip-select for DDR controller interleavingYork Sun
When DDR controller interleaving is eabled and less than all bank (chip-select) interleaving is seletected, the unused chip-select should be disabled. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-31Fix parameters to support RDIMM for P2020DSYork Sun
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/8xxx: Improvement to DDR parametersyork
Changes for P2020DS DDR applies to other 8xxx platform Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26powerpc/8xxx: Enable DDR3 RDIMM supportyork
Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26powerpc/8xxx: Enabled address hashing for 85xxyork
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26powerpc/8xxx: Enable quad-rank DIMMs.york
Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4york
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun <yorksun@freescale.com>
2010-04-26fsl-ddr: Add extra cycle to turnaround timesDave Liu
Add an extra cycle turnaround time to read->write to ensure stability at high DDR frequencies. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-21Move arch/ppc to arch/powerpcStefan Roese
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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