summaryrefslogtreecommitdiff
path: root/arch/powerpc
AgeCommit message (Collapse)Author
2011-04-04powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala
We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020Kumar Gala
Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"Pankaj Chauhan
In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala
Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add support for Integrated Flash Controller (IFC)Dipen Dudhat
The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Add SERDES support for P1010/P1014Prabhakar Kushwaha
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-29powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-28powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-27Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk
2011-03-27rename _end to __bss_end__Po-Yu Chuang
Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
2011-03-24powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134York Sun
The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-24powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-24powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-22Introduce a new linker flag LDFLAGS_FINALHaiying Wang
commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2011-03-15powerpc/85xx: Fix synchronization of timebase on MP bootKumar Gala
There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-13mpc8[5/6]xx: Ensure POST word does not get resetJohn Schmoller
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx processors. When interrupt_init() is called, this register gets reset which resulted in all POST_RAM POSTs not being ran due to the corrupted POST word. To resolve this, store off POST word before the PIC is reset, and restore it after the PIC has been initialized. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet PlatformsEd Swarthout
Copying directly from ECM/PQ3 is not correct for how CoreNet based platforms handle boot page translation. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-10powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun
When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-09Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2011-02-07ppc4xx: Add DLVision-10G board supportDirk Eibach
Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
2011-02-06Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2011-02-05mpc83xx: Use correct register to calculate clocks.Joakim Tjernlund
Use SPMR instead of HRCWL when calculating clocks as HCRWL may be changed and the CPU will not pick up all changes until there is a POR. u-boot will think SPMF has changed and get the clocks wrong. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-02-05mpc83xx: fix pcie configuration space read/writeLeo Liu
This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-02-04powerpc/8xxx: Fix possible compile issue related to P1013Kumar Gala
The P1013 is a single core version of P1022 and thus should use the p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which doesn't exist. Reported-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134York Sun
Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/85xx: Rename MPC8572 DDR erratum to DDR115York Sun
Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/85xx: Remove unnecessary polling loop from DDR initYork Sun
This polling loop is not required normally, unless specifically stated in workaround. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCsKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-02Minor Coding Style Cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-01-25Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGSNobuhiro Iwamatsu
Linker needs to use the proper endian/bfd flags even when doing partial linking. LDFLAGS_u-boot sets linker option which is called it when U-boot is built (u-boot final). LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target). CC: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-01-25Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2011-01-24powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala
ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBCDipen Dudhat
Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun
Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19corenet_ds: Extend board specific parametersYork Sun
Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc85xx: Implement workaround for erratum DDR-A003York Sun
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc85xx: Adding more registers and optionsYork Sun
This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc8xxx: Enable ECC on/off control in hwconfigYork Sun
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19mpc8xxx: Display RDIMM if detectedYork Sun
Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala
Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala
There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19powerpc/p2040: Add various p2040 specific informationKumar Gala
Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/p5020: Add various p5020 specific informationKumar Gala
Add P5020 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/p3041: Add various p3041 specific informationKumar Gala
Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal
The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit (git 2.34.1) at 2024-12-29 02:20:56 +0000