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path: root/arch/riscv/cpu/fu540
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2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04riscv: sifive: fu540: add SPL configurationPragnesh Patel
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel
Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>