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2019-04-08riscv: implement IPI platform functions using SBILukas Auer
The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: import the supervisor binary interface header fileLukas Auer
Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer
Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V because bootm will update initrd location in DTB only if CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable this option then bootm assumes DTB already has initrd details which is not the case most of the time. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel
This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot DMA mapping APIs will generate DMA addresses beyond 4GB. This breaks DMA programming in 32bit DMA capable devices (such as Cadence MACB ethernet). For example, If DRAM is more then 2GB on QEMU sifive_u machine then Cadence MACB ethernet stops working for U-Boot because it is a 32bit DMA capable device. To handle 32bit DMA capable devices on 64bit systems, we provide custom implementation of board_get_usable_ram_top() which ensures that usable ram top is not more then 4GB. This in-turn ensures that U-Boot always runs within 4GB hence DMA addresses generated by DMA mapping APIs will be within 4GB too. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel
Some of the drivers (such as Cadence MACB ethernet driver) expect asm/arch/clk.h to be provided by arch support so we add place-holder asm/arch-generic/clk.h for RISC-V generic CPU. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel
This patch adds asm/dma-mapping.h for Linux-like DMA mappings APIs required by some of the drivers (such as, Cadance MACB Ethernet driver). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15riscv: qemu: define standalone load addressLukas Auer
We need to define the standalone load address to use standalone application on qemu-riscv. Define it and set it equal to CONFIG_SYS_LOAD_ADDR. To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR in arch/riscv/config.mk to a conditional one. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15riscv: remove RISC-V standalone linker scriptLukas Auer
Standalone applications do not require a separate linker script and can use the default linker script of the compiler instead. Remove the RISC-V standalone linker script. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer
The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer
The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15riscv: clarify error message on undefined exceptionsLukas Auer
Undefined exceptions are treated as reserved. This is not clearly communicated to the user. Adjust the error message to clarify that a reserved exception has occurred and add additional details. Fixes: e8b522b ("riscv: treat undefined exception codes as reserved") Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-31riscv: bootm: Support booting VxWorksBin Meng
Register the 'bootm' function for booting VxWorks kernel for RISC-V architecture. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18riscv: Remove ae350.dtsBin Meng
This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng
Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Save boot hart id to the global dataBin Meng
At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add exception codes for xcause registerBin Meng
This adds all exception codes in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add CSR numbersBin Meng
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Probe cpus during bootBin Meng
This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng
Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel
This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel
So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng
There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-18riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng
To enumerate devices on the /soc/ node, create a "simple-bus" driver to match "riscv-virtio-soc". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer
RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-05riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen
ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE to boot from ram which allow the board to override the fdt address originally. But after this patch riscv: save hart ID and device tree passed by prior boot stage It provide prior_stage_fdt_address which offer a temporary memory address to keep the dtb address passing from loader(gdb) to u-boot with a1. So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and can be removed. And it also somehow may corrupted BBL if it was be arranged in CONFIG_SYS_SDRAM_BASE. In board_fdt_blob_setup() When boting from ram: prior_stage_fdt_address will be use to reserved dtb temporarily. When booting from ROM: dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base. Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM) which is provided by HW. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-02riscv: efi: Generate Microsoft PE format compliant imagesBin Meng
Per Microsoft PE Format documentation [1], PointerToSymbolTable and NumberOfSymbols should be zero for an image in the COFF file header. Currently the COFF file header is hardcoded on RISC-V and these two members are not zero. This updates the hardcoded structure to clear these two members, as well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we can generate compliant *.efi images. [1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-26riscv: dts: Add ae350_32.dts for RV32IRick Chen
Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-26riscv: dts: Sync to Linux Kernel ae350 dts.Rick Chen
Use same dts to boot U-Boot and Kernel. Following are the change notes : 1 Remove early printk bootargs. 2 Timer frequency are changed to 60MHz. 3 Add dma, snd, lcd, virtio nodes which are used in kernel drivers. They does not been used by U-Boot. 4 Change spi irq from 3 to 4. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-26riscv: align bootm implementation with that of other architecturesLukas Auer
The bootm implementation of RISC-V diverges from that of other architectures. Update it to match the implementation of other architectures. The ARM implementation is used as a reference. This adds the following features and changes to RISC-V. * Add support for the BOOTM_STATE_OS_FAKE_GO command * Call the remove function on devices with the removal flag set before booting Linux * Force disconnect USB devices from the host before booting Linux * Print and add bootstage information to the device tree before booting Linux Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer
Store the hart ID and device tree passed by the prior boot stage (in a0 and a1) in registers s0 and s1. Replace one use of s1 in start.S to avoid overwriting it. The device tree is also stored in memory to make it available to U-Boot with the configuration CONFIG_OF_PRIOR_STAGE. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: do not blindly modify the mstatus CSRLukas Auer
The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for U-Boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26riscv: remove unused labels in start.SLukas Auer
The labels nmi_vector, trap_vector and handle_reset in start.S are not used for RISC-V. Remove them. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26Drop CONFIG_INIT_CRITICALBin Meng
This is now deprecated and no board is using it. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-11-26riscv: align mtvec on a 4-byte boundaryLukas Auer
The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer
start.S uses both tabs and spaces after instructions. Fix this by only using tabs after instructions. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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