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2018-03-30riscv: dts: AE250 support sd High-Speed modeRick Chen
Enable High-Speed mode with cap-sd-highspeed in dts. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: bootm: Remove ATAGSRick Chen
ATAGS is not supported and will be replaced by DT in riscv-linux. So can be removed now. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: bootm: Support to boot riscv-linuxRick Chen
riscv-linux should use BBL (Berkeley bootloader) for loading the Linux kernel. U-Boot can play as FSBL(first stage bootloader) to boot BBL and riscv-linux. In BBL's init_first_hart(), it will pass dtb with a1. So implement bootm to pass arguments to BBL correctly. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: checkpatch: Fix static const char * array declarationsRick Chen
It is reported by checkpatch.pl WARNING: static const char * array should probably be static const char * const Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: checkpatch: Fix missing a blank line after declarationsRick Chen
It is reported by checkpatch.pl WARNING: Missing a blank line after declarations. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: checkpatch: Fix alignment should match open parenthesisRick Chen
It is reported by checkpatch.pl. CHECK: Alignment should match open parenthesis Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: checkpatch: Fix use of volatileRick Chen
It is reported by checkpatch.pl WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30riscv: checkpatch: Fix Macro argument reuseRick Chen
It is CHECK reported by checkpatch.pl CHECK: Macro argument reuse 'PTE' - possible side-effects? Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: nx25: include: Add header files to support RISC-VRick Chen
Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: dts: Add AE250 dts to support RISC-VRick Chen
AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: lib: Add relative lib funcs to support RISC-VRick Chen
Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: cpu: Add nx25 to support RISC-VRick Chen
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
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