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2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass
Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add power-control supportSimon Glass
Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add reference code supportSimon Glass
Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add an LPC driverSimon Glass
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a northbridge driverSimon Glass
Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a SATA driverSimon Glass
Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass
GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a PCH driverSimon Glass
Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add basic support for broadwellSimon Glass
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass
Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Record the CPU details when starting each coreSimon Glass
As each core starts up, record its microcode version and CPU ID so these can be presented with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass
At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass
Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass
This same name is used in USB. Add a prefix to distinguish it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common CPU code to its own placeSimon Glass
Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common LPC code to its own placeSimon Glass
Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass
This is similar to MCH in that it is used in various drivers. Add it to the common header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Create a common header for Intel register accessSimon Glass
There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move microcode code to a common locationSimon Glass
This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass
These two identifiers can be useful for drivers which need to adjust their behaviour depending on the CPU family or stepping (revision). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add comments to the SIPI vectorSimon Glass
The Intel SIPI (start-up inter-processor interrupt) vector is the entry point for each secondary CPU (also called an AP - applications processor). The assembler and C code are linked, so add comments to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass
The timeout step is always 50us. By updating apic_wait_timeout() to print the debug messages we can simplify the code. Also tidy up a few messages and comments while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add some more common MSR indexesSimon Glass
Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: cpu: Make the vendor table constSimon Glass
This does not need to be modified at run-time, so make it const. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Change write_acpi_tables() signature a little bitBin Meng
Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that coreboot table definitions can be used by other x86 builds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-14dm: Use uclass_first_device_err() where it is usefulSimon Glass
Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: Add Intel Cougar Canyon 2 boardBin Meng
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: ivybridge: Add FSP supportBin Meng
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: fix memalign() parameter orderStephen Warren
Purely by code inspection, it looks like the parameter order to memalign() is swapped; its parameters are (align, size). 4096 is a likely desired alignment, and a variable named size sounds like a size:-) Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-08Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini
2016-02-06Use correct spelling of "U-Boot"Bin Meng
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-05x86: quark: Use Quark's own PCI config APIsBin Meng
There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: pci: Drop legacy PCI APIsBin Meng
Now that we have converted all x86 codes to use DM PCI APIs, drop those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: pci: Use DM PCI APIs in pci_assign_irqs()Bin Meng
Drop legacy PCI APIs usage in pci_assign_irqs() as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: qemu: Convert to use DM PCI APIBin Meng
Use pci_[read|write]_config intead of x86_pci_[read|write]_config. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng
With recent DM PCI changes to vesa_fb driver, external graphics card does not work any more. This is because: after setting the function disable bit, IGD and SDVO devices will disappear in the PCI configuration space. This however creates an inconsistent state from a driver model PCI controller point of view, as these two PCI devices are still attached to its parent's child device list as maintained by the driver model. Some driver model PCI APIs like dm_pci_find_class() used in the vesa_fb driver, are referring to the list to speed up the finding process instead of re-enumerating the whole PCI bus, so it gets the stale cached data which is wrong. To fix this, manually remove these two devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Use DM PCI API in disable_igd()Bin Meng
Once we get udevice of IGD and SDVO, we can use its udevice to access PCI configuration space with dm_pci_write_config32(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Change disable_igd() to have a return valueBin Meng
So far disable_igd() does not have any return value, but we may need that in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: irq: Convert to use DM PCI APIBin Meng
Now that we have irq router's udevice passed as a parameter, it's time to start using the DM PCI API instead of those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: irq: Move irq_router to a per driver privBin Meng
At present irq_router is declared as a static struct irq_router in arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense to move it to a per driver priv. Adjust existing APIs to accept an additional parameter of irq_router's udevice. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: irq: Get irq_router's bdf via dm_pci_get_bdf()Bin Meng
There is no need to parse PCH's <reg> property as we have already a DM PCI API dm_pci_get_bdf() that can handle this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: pch: Implement get_gpio_base opBin Meng
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Rename get_sbase op to get_spi_baseBin Meng
Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Remove pch_get_version opBin Meng
pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: quark: Drop unprotect_spi_flash()Bin Meng
Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Drop unprotect_spi_flash()Bin Meng
Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-12-29 19:17:33 +0000