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2019-09-10x86: tangier: Fix off-by-one error when preparing CSRTAndy Shevchenko
Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko
Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: show UEFI images involved in crashHeinrich Schuchardt
If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[<fec9906e>] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: qemu: Report high memory in the E820 tableBin Meng
Now that we are able to get the size of high memory from QEMU, report its memory range as usable ram. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Support getting high memory sizeBin Meng
At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Extract getting memory size to a separate routineBin Meng
This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-08-18x86: Remove x86 specific GD flags as they are not referenced at allStefan Roese
This patch removes the x86 architecture specific GD flags (GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S. But the coreboot target does not use start16.S at all and boots directly from the 32-bit start code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11env: Rename environment.h to env_internal.hSimon Glass
This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-11env: Move TOTAL_MALLOC_LEN to environment.hSimon Glass
This declaration is only used in three files. Although it relates to malloc() it is actually only used during malloc() init. It uses CONFIG options including CONFIG_ENV_ADDR which are defined only in environment.h so this header must be included anyway, for TOTAL_MALLOC_LEN to be correct. Nove it to environment.h to simplify the common file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-09x86: slimbootloader: Set TSC information for tsc_timerPark, Aiden
Slim Bootloader already calibrated TSC and provides it to U-Boot. Therefore, U-Boot does not have to re-calibrate TSC. Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass TSC calibration and use the provided TSC frequency. - Get TSC frequency from performance info hob - Set tsc_base and clock_rate for tsc_timer driver Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add serial driverPark, Aiden
Slim Bootloader provides serial port info thru its HOB list pointer. All these HOBs are eligible for Slim Bootloader based board only. - Get serial port information from the serial port info HOB - Leverage ns16550 driver with slimbootloader specific platform data Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add memory configurationPark, Aiden
Slim Bootloader provides memory map info thru its HOB list pointer. Configure memory size and relocation memory from the HOB data, and provide e820 entries as well. - Get memory size from the memory map info HOB - Set available top memory lower than 4GB for U-Boot relocation - Provide e820 entries from the memory map info HOB Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add new slimbootloader CPU typePark, Aiden
This slimbootloader CPU type is to enable U-Boot as a payload which runs on top of Slim Bootloader (https://github.com/slimbootloader). The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS booting, and supports QEMU, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP (https://github.com/IntelFsp) for silicon initialization including CAR and memory initialization. The Slim Bootloader generates new HOB (Hand Off Block) which are serial port info, memory map info, performance data info and so on, and passes it to a Payload. U-Boot as a payload will use these HOB information for basic initialization such as serial console. As an initial commit, - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type - Add new arch/x86/cpu/slimbootloader directory with minimum codes - Get hob_list pointer from Slim Bootloader Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: tangier: Populate CSRT for shared DMA controllerAndy Shevchenko
Intel Tangier has a shared DMA controller that, according to Microsoft spec, has to be presented in CSRT table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-22watchdog: tangier: Convert to use WDT classAndy Shevchenko
Convert legacy driver to use watchdog class. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-19x86: coreboot: make it possible to process unhandled tagsChristian Gmeiner
coreboot makes it possible to add own entries into coreboot's table at a per mainboard basis. As there might be some custom ones it makes sense to provide a way to process them. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-09Fix spelling of available.Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2019-05-08x86: Add a way to jump from TPL to SPLSimon Glass
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Update PCH to work in TPLSimon Glass
The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support TPL in Intel common codeSimon Glass
Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add common Intel code for SPLSimon Glass
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Select refcode and CPU code for SPLSimon Glass
Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow booting from SPLSimon Glass
At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Allow 16-bit init to be in TPLSimon Glass
At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add support for starting from SPL/TPLSimon Glass
When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Split CPU initSimon Glass
Split the CPU init into two parts - the 'full' init which happens in the first U-Boot phase, and the rest of the init that happens on subsequent stages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Move init of debug UART to cpu.cSimon Glass
At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow SDRAM init from SPLSimon Glass
At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported. Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Improve SDRAM debugging outputSimon Glass
Add debugging during SDRAM init so that problems are easier to diagnose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a way to reinit the cpuSimon Glass
We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: mp_init: Use proper error numbersSimon Glass
At present many of the functions in this file return -1 as an error number. which is -EPERM. Update the code to use real error numbers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update a stale comment about ifdtoolSimon Glass
We use binman to build the x86 image now. Update a comment which still refers to ifdtool. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: start64: Fix copyright messageSimon Glass
There is a typo in this header. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Add support for serial I/O devicesSimon Glass
Add support for initing the I2C device and ADSP on broadwell. These are needed for sound to work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Don't bother probing the PCH for pinctrlSimon Glass
At present the pinctrl probes the PCH but since it only uses it to obtain a PCI address, this is no necessary. Avoiding this fixes one of the two co-dependent loops in broadwell. This driver really should be a proper pinctrl driver, but for now it remains a syscon device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Add support for the ADSPSimon Glass
The Application Digital Signal Processor is used for sound processing with broadwell. Add a driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: link: Add sound supportSimon Glass
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: ivybridge: Add a way to get the HDA config settingSimon Glass
Add a way check to whether HD audio is enabled. Use ioctl() to avoid adding too many unusual operations to PCH. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12x86: Use the existing GDT in the ROM for 64-bit U-Boot properBin Meng
It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper. In fact we can just use the ROM version directly, which not only eliminates the risk of being overwritten by application, but also removes the complexity of patching the cpu_call64(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12x86: Don't copy the cpu_call64() function to a hardcoded addressBin Meng
Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64() function to a hardcoded address 0x3000000. This can have potential conflicts with application usage. Switch the destination address to be allocated from the heap to avoid such risk. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12x86: Change 4-level page table base address to low memoryBin Meng
At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-26linker: Modify linker scripts to be more genericTom Rini
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the same script for both SPL and TPL. Add logic to scripts/Makefile.spl to pass in the right value when preprocessing the script. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-18x86: Kconfig: spelling fixesChris Packham
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-10efi: payload: only init usb if necessaryBin Meng
Up until now the call to initialize the USB subsystem was hardcoded for U-Boot running as an EFI payload. This was used to enable the use of a USB keyboard in the U-Boot shell. However not all boards might need this functionality. As initializing the USB subsystem can take a considerable amount of time (several seconds on some boards), we now initialize the USB subsystem only if U-Boot is configured to use USB keyboards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-12-10coreboot: only init usb if necessaryThomas RIENOESSL
Up until now the call to initialize the USB subsystem was hardcoded for U-Boot running as a coreboot payload. This was used to enable the use of a USB keyboard in the U-Boot shell. However not all boards might need this functionality. As initializing the USB subsystem can take a considerable amount of time (several seconds on some boards), we now initialize the USB subsystem only if U-Boot is configured to use USB keyboards. Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-12-10x86: make the LAPIC / IOAPIC construct switchable with KconfigHannes Schmelzer
There are still systems running which do not have any LAPIC or even IOAPIC. Responsible MSRs for those do not exist and the systems are crashing on trying to setup LAPIC. This commit makes the APIC stuff able to switch off for those boards which dont' have an LAPIC / IOAPIC. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-14cpu: Add DM_FLAG_PRE_RELOC flag to various cpu driversBin Meng
It turns out commit c0434407b595 broke some boards which have DM CPU driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail to boot when print_cpuinfo() is called during boot. Fixes: c0434407b595 ("board_f: Use static print_cpuinfo if CONFIG_CPU is active") Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2018-11-14sysreset: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-13 16:41:58 +0000