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2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop asm/ptrace.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop bootstage.h from common headerSimon Glass
Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18part: Drop disk_partition_t typedefSimon Glass
We should not be using typedefs and these make it harder to use forward declarations (to reduce header file inclusions). Drop the typedef. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-04x86: coreboot: Allow building an SPL imageSimon Glass
Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Move work-around out of cpu_jump_to_64bit_uboot()Simon Glass
At present this function copies U-Boot from the last 1MB of ROM. This is not the right way to do it. Instead, the binman symbol should provide the location. But in any case the code should live in the caller, spl_board_load_image(), so that the 64-bit jump function can be used elsewhere. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Allow building an SPL image for corebootSimon Glass
Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add a build rule and binman definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Move coreboot-table detection to common 32/64-bit codeSimon Glass
At present this function is only available in 32-bit code. Move it to the common cpu file so it can be used by 64-bit U-Boot too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Use the existing stack when chain-loadingSimon Glass
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Add a way to detect running from corebootSimon Glass
If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Move coreboot-table detection into common codeSimon Glass
To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: cpu: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: apl: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the FSP-S init must be skipped. Update it to add a check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16x86: Move acpi_table header to main include/ directorySimon Glass
This file is potentially useful to other architectures saddled with ACPI so move most of its contents to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-16x86: Move acpi_s3.h to include/acpi/Simon Glass
This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16x86: apl: Move p2sb ofdata reading to the correct methodSimon Glass
With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-16x86: Correct wording of coreboot source codeSimon Glass
Some files are taken or modified from coreboot, but the files are no-longer part of the coreboot project. Fix the wording in a few places. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-03-05x86: apl: Use cpu_x86_get_count() for cpu_ops.get_countWolfgang Wallner
Use cpu_x86_get_count() to read the number of cores. cpu_x86_get_count() reads the number of CPUs from the device tree. Using this function we can support multiple Apollo Lake variants, e.g.: E3940 (4 cores) and E3930 (2 cores). This was tested on the E3940 and E3930 Apollo Lake variants. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: cpu_x86: Make cpu_x86_get_count() non-staticWolfgang Wallner
The function cpu_x86_get_count() is also useful for other modules. Make it non-static and add a prototype + description. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: p2sb: Drop 'apl' prefixWolfgang Wallner
Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05Revert "x86: use invd instead of wbinvd in real mode start code"Andy Shevchenko
This reverts commit 0d67fac29f3187e67f4fd3ef15f73e91be2fad12. As real hardware testing (*) shows the above mentioned commit breaks U-Boot on it. Revert for the upcoming release. We may get more information in the future and optimize the code accordingly. (*) on Intel Edison board. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-07x86: coral: Add I2C and TPM device-tree definitionsSimon Glass
Add nodes to the device tree for Cr50 and other available I2C ports. Also enable the ACPI interrupt driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Add support for ACPI general-purpose eventsSimon Glass
ACPI GPEs are used to signal interrupts from peripherals that are accessed via ACPI. In U-Boot these are modelled as interrupts using a separate interrupt controller. Configuration is via the device tree. Add a simple driver for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: itss: Add of-platdata supportSimon Glass
Allow this driver to be used in TPL by setting up the interrupt type correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Give each driver an IRQ typeSimon Glass
Add an IRQ type to each driver and use irq_first_device_type() to find and probe the correct one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: apl: Drop the I2C config in FSP-SSimon Glass
This config is not actually used here and in U-Boot it seems better to set this using the device tree for each individual controller. The monolithic config of the FSP-S is only necessary if the FSP is actually configuring something, but here it is not. The FSP-S does enable/disable the various I2C ports. It might be nice to handle this using the okay/disabled property of each port, but that can be considered later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: apl: Use the clock driverSimon Glass
Enable the Intel clock driver and modify coral's device tree to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Move P2SB from Apollo Lake to a more generic locationWolfgang Wallner
The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-04x86: itss: Remove apl-prefixWolfgang Wallner
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so remove the apl-prefix of the implemented functions/structures/... Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner
Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner
The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner
ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: limit the fs segment to the pointer sizeMasahiro Yamada
The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the comments about FS segement] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: use invd instead of wbinvd in real mode start codeMasahiro Yamada
I do not know why the boot code immediately after the system reset should write-back the cache content. I think the cache invalidation should be enough. I tested this commit with qemu-x86_defconfig, and it worked for me. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: serial: Use NS16550_DYNAMIC in Slim BootloaderPark, Aiden
Slim Bootloader provides serial port info in its HOB to support both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 or SYS_NS16550_PORT_MAPPED in U-Boot. To support both serial port configurations dynamically at runtime, Slim Bootloader serial driver leverages NS16550_DYNAMIC. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove the obsolete comments for data->type] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-17common: Move hang() to the same header as panic()Simon Glass
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move ll_boot_init() to init.hSimon Glass
This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07x86: apl: Avoid accessing the PCI bus before it is probedSimon Glass
The PCI bus is not actually probed by the time the ofdata_to_platdata() method is called since that happens in the uclass's post_probe() method. Update the PMC and P2SB drivers to access the bus in its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-15x86: apl: Add FSP supportSimon Glass
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add Kconfig and MakefileSimon Glass
Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add P2SB driverSimon Glass
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-01-02 19:36:09 +0000