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2019-10-08x86: Rename some FSP functions to have an fsp_ prefixSimon Glass
Given these exported function an fsp_ prefix since they are declared in an fsp.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_ffs.h include to fsp_arch.hSimon Glass
This include file is only used for FSP v1. Avoid including it from fdt_support.h so we can use the latter with FSP v2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_bootmode.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2, although there may be some additions to come. Move it into the generic fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_infoheader.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: move rename of fsp_infoheader.h from previous patch to this one] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_hob.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove inclusion of fsp_hob.h in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_fv.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_types.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_api.h inclusion out of fsp_support.hSimon Glass
This header file is different for each version of FSP. Move it into the fsp_arch.h header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Create a new fsp_arch.h headerSimon Glass
At present fsp_support.h includes fsp_vpd.h which is an FPSv1 concept (VPD means Vital Product Data). For FSPv2 only UPD (Updatable Product Data) is used. To avoid mangling header files, put these two includes in a separate header which we can adjust as necessary for FSPv2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_azalia.h to the generic fsp directorySimon Glass
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-01x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parametersAndy Shevchenko
This is reincarnation of the U-Boot commit 3469bf4274540d1491d58e878a9edc0bdcba17ac Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Wed Jan 10 19:40:15 2018 +0200 x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters after upstream got eventually the Linux kernel commit e6e094e053af75cbc164e950814d3d084fb1e698 Author: Juergen Gross <jgross@suse.com> Date: Tue Nov 20 08:25:29 2018 +0100 x86/acpi, x86/boot: Take RSDP address from boot params if available Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Use spaces over TABs in ASL codeAndy Shevchenko
For sake of consistency use spaces over TABs in ASL code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko
Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: acpi: Annotate struct acpi_table_header with __packedAndy Shevchenko
GCC 9.2 starts complaining about possible pointer misalignment of pointers to the unpacked (alignment=4) structures in the packed (alignment=1) ones: CC arch/x86/cpu/tangier/acpi.o arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’: arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed member of ‘struct acpi_fadt’ may result in an unaligned pointer value [-Waddress-of-packed-member] 22 | struct acpi_table_header *header = &(fadt->header); CC arch/x86/lib/acpi_table.o arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’: arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed member of ‘struct acpi_spcr’ may result in an unaligned pointer value [-Waddress-of-packed-member] 366 | struct acpi_table_header *header = &(spcr->header); Fix the potential issues by annotating embedded structures with __packed even though they are packed naturally. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add GCC version number in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: qemu: Support getting high memory sizeBin Meng
At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Extract getting memory size to a separate routineBin Meng
This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: acpi: Slightly reduce binary size of ACPI tables for TangierAndy Shevchenko
Using ACPI predefined macros, such as Zero or One, will reduce a binary size of resulting ACPI tables. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: manually fixed the conflicts when applying] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18x86: Remove x86 specific GD flags as they are not referenced at allStefan Roese
This patch removes the x86 architecture specific GD flags (GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S. But the coreboot target does not use start16.S at all and boots directly from the 32-bit start code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-09x86: slimbootloader: Set TSC information for tsc_timerPark, Aiden
Slim Bootloader already calibrated TSC and provides it to U-Boot. Therefore, U-Boot does not have to re-calibrate TSC. Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass TSC calibration and use the provided TSC frequency. - Get TSC frequency from performance info hob - Set tsc_base and clock_rate for tsc_timer driver Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add serial driverPark, Aiden
Slim Bootloader provides serial port info thru its HOB list pointer. All these HOBs are eligible for Slim Bootloader based board only. - Get serial port information from the serial port info HOB - Leverage ns16550 driver with slimbootloader specific platform data Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add memory configurationPark, Aiden
Slim Bootloader provides memory map info thru its HOB list pointer. Configure memory size and relocation memory from the HOB data, and provide e820 entries as well. - Get memory size from the memory map info HOB - Set available top memory lower than 4GB for U-Boot relocation - Provide e820 entries from the memory map info HOB Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add a common HOB libraryPark, Aiden
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER) consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer. Add a common HOB library in lib/hob.c and include/asm/hob.h. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: lib: fsp: Use EFI_GUID and efi_guid_tPark, Aiden
Use existing EFI_GUID and efi_guid_t instead of struct efi_guid. This is pre-work before making a common HOB library. - Change 'struct efi_guid' to efi_guit_t - Remove 'struct efi_guid' - Define GUIDs with EFI_GUID() macro - Use guidcmp() instead of compare_guid() - Remove compare_guid() Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested on MinnowMax Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add new slimbootloader CPU typePark, Aiden
This slimbootloader CPU type is to enable U-Boot as a payload which runs on top of Slim Bootloader (https://github.com/slimbootloader). The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS booting, and supports QEMU, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP (https://github.com/IntelFsp) for silicon initialization including CAR and memory initialization. The Slim Bootloader generates new HOB (Hand Off Block) which are serial port info, memory map info, performance data info and so on, and passes it to a Payload. U-Boot as a payload will use these HOB information for basic initialization such as serial console. As an initial commit, - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type - Add new arch/x86/cpu/slimbootloader directory with minimum codes - Get hob_list pointer from Slim Bootloader Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: acpi: Enable ACPI companion for Intel iDMA 32-bitAndy Shevchenko
ACPI has a capability to specify DMA parameters for DMA channel consumers. To enable this for Intel Edison, describe GP DMA device in ACPI table in order to get an ACPI handle to it in OS. This works in conjunction with CSRT, which must be in align with DSDT. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: acpi: Introduce a stub to generate CSRTAndy Shevchenko
Here is a stub function that generates an empty CSRT. If the target platform provides acpi_fill_csrt() function, it will be used to populate the table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: acpi: Add CSRT descriptionAndy Shevchenko
Add CSRT [1] description as it provided in Linux kernel. [1]: http://www.uefi.org/sites/default/files/resources/CSRT%20v2.pdf Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10x86: Add a forward struct declaration in coreboot_tables.hSimon Glass
This struct is not defined in this header file. Add a forward declaration so that it can be included in any context. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a simple TPL implementationSimon Glass
Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support saving MRC data from SPLSimon Glass
When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a handoff header fileSimon Glass
Add an arch-specific handoff header so that we can use the HANDOFF feature on x86 devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a way to reinit the cpuSimon Glass
We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10x86: acpi: Add DMA descriptors for I2C1 on Intel TangierAndy Shevchenko
Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10x86: acpi: Add DMA descriptors for SPI5 on Intel TangierAndy Shevchenko
Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Add support for serial I/O devicesSimon Glass
Add support for initing the I2C device and ADSP on broadwell. These are needed for sound to work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Add support for the ADSPSimon Glass
The Application Digital Signal Processor is used for sound processing with broadwell. Add a driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: Add beeping support in i8254Simon Glass
Adjust the code to allow beeping at different frequencies, using a calculated value for timer 2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: link: Add sound supportSimon Glass
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: Adjust I/O macros to work on 64-bit machinesSimon Glass
At present these macros give warnings on 64-bit machines and do not correctly do 32-bit accesses. Update them to use linux types. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-13x86: do not use i386 code for x86_64 memory functionsHeinrich Schuchardt
arch/x86/lib/string.c contains assembler implementations of memcpy(), memmove(), and memset() written for i386. Don't use it on x86_64. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-12x86: tangier: Add initial ACPI support for PMIC deviceAndy Shevchenko
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10x86: acpi: Fix indentation in Intel Tangier ASL codeAndy Shevchenko
Make the indentation aligned with what used elsewhere in U-Boot. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10x86: acpi: Enable RTC for Intel TangierAndy Shevchenko
Intel Tangier SoC has RTC inside. So, enable it in ACPI. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-05x86: acpi: Generate SPCR tableAndy Shevchenko
Microsoft specifies a SPCR (Serial Port Console Redirection Table) [1]. Let's provide it in U-Boot. [1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-05x86: acpi: Add SPCR table descriptionAndy Shevchenko
Add SPCR table description as it provided in Linux kernel. Port subtype for ACPI_DBG2_SERIAL_PORT is used as an interface type in SPCR. Thus, provide a set of definitions to be utilized later. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-14x86: Implement arch-specific io accessor routinesBin Meng
At present the generic io{read,write}{8,16,32} routines only support MMIO access. With architecture like x86 that has a separate IO space, these routines cannot be used to access I/O ports. Implement x86-specific version to support both PIO and MMIO access, so that drivers for multiple architectures can use these accessors without the need to know whether it's MMIO or PIO. These are ported from Linux kernel lib/iomap.c, with slight changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-06x86: acpi: Remove redundant Offset (0x00)Andy Shevchenko
New ACPI assembler issues a warning: board/intel/edison/dsdt.asl.tmp 13: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Indeed, in the OperationRegion the offset is 0x00 by default. Thus, drop unneeded Offset() use as suggested by ACPI assembler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / regionStefan Roese
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch changes the base address and range of the ACPI area passed to Linux. BayTrail can only physically access 36 bit of PCI address space. So just chaning the range without changing the base address won't work here, as 0xf.ffff.ffff is already the maximum address. With this patch, a maximum of 16 GiB of local DDR is supported. This should be enough for all BayTrail boards though. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09x86: Update mtrr functions to allow leaving cache aloneSimon Glass
At present the mtrr functions disable the cache before making changes and enable it again afterwards. This is fine in U-Boot, but does not work if running in CAR (such as we are in SPL). Update the functions so that the caller can request that caches be left alone. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-01-12 21:58:33 +0000