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2019-09-12armv8: ls1028a: configure PMU's PCTBENR to enable WDTThomas Schaefer
The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12arm: dts: ls1028a-qds: define the MDIO MUXAlex Marginean
Add the device-tree structure describing the MUX in board dts. QDS board has an on-board RGMII PHY and 4 slots for extension cards. All these can be accessed over MDIO through a MDIO MUX controlled over I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12dts: armv8: add emmc hs200 support for ls1028ardbYinbo Zhu
Add emmc hs200 support for ls1028ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12dts: armv8: add emmc hs200 support for lx2160ardbYinbo Zhu
Add emmc hs200 support for lx2160ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12dts: armv8: add emmc hs200 support for ls1012ardbYinbo Zhu
Add emmc hs200 support for ls1012ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12fsl-layerscape: Add fsl_esdhc peripheral clock supportYinbo Zhu
Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-10x86: tangier: Use spaces over TABs in ASL codeAndy Shevchenko
For sake of consistency use spaces over TABs in ASL code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Fix off-by-one error when preparing CSRTAndy Shevchenko
Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko
Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: acpi: Annotate struct acpi_table_header with __packedAndy Shevchenko
GCC 9.2 starts complaining about possible pointer misalignment of pointers to the unpacked (alignment=4) structures in the packed (alignment=1) ones: CC arch/x86/cpu/tangier/acpi.o arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’: arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed member of ‘struct acpi_fadt’ may result in an unaligned pointer value [-Waddress-of-packed-member] 22 | struct acpi_table_header *header = &(fadt->header); CC arch/x86/lib/acpi_table.o arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’: arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed member of ‘struct acpi_spcr’ may result in an unaligned pointer value [-Waddress-of-packed-member] 366 | struct acpi_table_header *header = &(spcr->header); Fix the potential issues by annotating embedded structures with __packed even though they are packed naturally. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add GCC version number in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: efi_loader: Use efi_add_conventional_memory_map()Park, Aiden
Use efi_add_conventional_memory_map() to configure EFI conventional memory properly with ram_top value. This will give 32-bit mode U-Boot proper conventional memory regions even if e820 has an entry which is greater than 32-bit address space. Signed-off-by: Aiden Park <aiden.park@intel.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> [bmeng: fixed some typos in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: show UEFI images involved in crashHeinrich Schuchardt
If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[<fec9906e>] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: qemu: Report high memory in the E820 tableBin Meng
Now that we are able to get the size of high memory from QEMU, report its memory range as usable ram. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Support getting high memory sizeBin Meng
At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Extract getting memory size to a separate routineBin Meng
This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: Drop weak version board_get_usable_ram_top()Bin Meng
Every x86 platform provides board_get_usable_ram_top(), hence there is no need to provide a weak version board_get_usable_ram_top(), not to mention there is another weak version board_get_usable_ram_top() in common/board_f.c. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: acpi: Slightly reduce binary size of ACPI tables for TangierAndy Shevchenko
Using ACPI predefined macros, such as Zero or One, will reduce a binary size of resulting ACPI tables. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: manually fixed the conflicts when applying] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-08Merge tag 'mmc-9-6-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
Bug fixes to mmc_spi Add Aspeed SD driver Fix dw_mmc timeout calculation Fix timeout values passed to mmc_wait_dat0 sdhci dt caps/mask update [trini: Fix evb-ast2500_defconfig CONFIG_MMC line] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-09-07Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Initial DM conversion
2019-09-06Merge tag 'rpi-next-2019.10' of https://github.com/mbgg/u-bootTom Rini
- fix mailbox status register used for polling - fix bcm2835_sdhost to wait long enough for a transfer to complete - increase kernel image size from 8 MB to 64 MB on arm64 - add support for RPi4 - add prefixes for raspberry pi related stuff to git-mailrc
2019-09-06ARM: bcm283x: Include definition for additional emmc clockAndrei Gherzan
This clock has a different mbox ID so have this included in the relevant header file. Signed-off-by: Andrei Gherzan <andrei@balena.io> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-06ARM: bcm283x: Define configs for RaspberryPi 4Andrei Gherzan
Define two target configs for Raspberry Pi 4 (32 and 64bit) and the corresponding BCM2838* configs. Be aware of the current limitation in firmware which requires an explicit configuration to force the arm in 64bit mode when the respective target is used. Signed-off-by: Andrei Gherzan <andrei@balena.io> [mb: rename BCM2838 -> BCM2711] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-06ARM: bcm283x: Add BCM283x_BASE defineMatthias Brugger
Devices of bcm283x have different base address, depending if they are on bcm2835 or bcm2836/7. Use BCM283x_BASE depending on the SoC you want to build and only add the offset in the header files. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Andrei Gherzan <andrei@balena.io>
2019-09-06ARM: bcm283x mbox: Fix send status registerFabian Vogt
Before we can send a message to the mailbox we have to check that there is space to do so. Therefore we poll the status register. But up to now the wrong status register, the one of mailbox 0, was checked. Fix this by polling the status regiser of mailbox 1. Signed-off-by: Fabian Vogt <fvogt@suse.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> [mb: rename registers and update commit message] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-09-05ARM: dts: ast2500: Add SDHCI nodesEddie James
Add nodes for the Aspeed SD controllers with their necessary properties. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05mmc: Add Aspeed SD controller driverEddie James
Add support for the Aspeed SD host controller engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-05clk: aspeed: Add support for SD clockEddie James
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-04arm: dts: Set custom names for cp110 master/slave MDIO busesAlex Marginean
Implicitly Marvell MDIO driver uses DT node names for devices, but in this case that is not unique. Set MDIO device names for master/slave to cpm/cps. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04drivers/fsl-mc: Create Kconfig file to manage driver specific configs betterFlorinel Iordache
Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-03Merge tag 'arc-for-2019.10-rc4' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc These are some very late changes mostly required to get 64-bit division working on ARC boards. For that we had to import missing parts of libgcc and add compiler flags to EMSDP which otherwise used very simple profile for compliation. And while at it another fix for EM SDP initialization is inluded as well.
2019-09-03arc: libgcc: Import __udivdi3 & __udivmoddi4 to allow 64-bit divisionAlexey Brodkin
As reported by Kever here [1] we were unable to compile 64-bit division code due to missing definition of __udivdi3(). Import its implementation and __udivmoddi4() as its direct dependency from today's libgcc [2]. [1] https://patchwork.ozlabs.org/patch/1146845/ [2] https://github.com/gcc-mirror/gcc/commit/5d8723600bc0eed41226b5a6785bc02a053b45d5 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Kever Yang <kever.yang@rock-chips.com>
2019-09-03Merge tag 'for-v2019.10-v2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2019.10 take 2 - i2c: mxc: add CONFIG_CLK support If CONFIG_CLK is enabled use clk framework for clock settings.
2019-09-03riscv: cache: use CCTL to flush d-cacheRick Chen
Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: dts: move out AE350 L2 node from cpus nodeRick Chen
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen
Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen
Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: andes_plic: init plic by scanning each cpu nodeRick Chen
Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe marked as unavailable, but the cpu node exists indeed. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: update fix_rela_dynMarcus Comstedt
The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com>
2019-09-02sh: r2dplus: Switch to DM PCI driverMarek Vasut
Add DT entry for the DM PCI driver, update board configs and drop ad-hoc board init code for the PCI bus. Instead, let the DM PCI driver initialize and operate the hardware. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02sh: r2dplus: Enable OF controlMarek Vasut
Enable OF control for SH4 R2Dplus board. This is necessary, because the PCI uclass is designed in a way that makes it depend on DT and disallows instanciating devices without DT (e.g. with platdata). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02sh: Fix OF_SEPARATE supportMarek Vasut
If the OF_SEPARATE is enabled, the DT is appended past the _end symbol. The current code however clears BSS very early, which overwrites the DT blob with zeroes. Moreover, the early code relocates U-Boot into RAM to the correct location, but does not relocate the DT. This patch adds code to relocate the DT and avoids clearing BSS too early, thus addressing both problems with OF_SEPARATE on SH. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02sh: tmu: Fix SH4 TCNT0 offsetMarek Vasut
Fix the offset of TCNT0 register, which is 0xc on SH4. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-02i2c: mxc: add CONFIG_CLK supportPeng Fan
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-09-01Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- r8a66597 usb changes
2019-08-31Revert "vexpress64: fvp dram: add DRAM configuration"Ryan Harkin
This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the FVP DRAM configuration was added. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-30board_f: fix noncached reservation calculationStephen Warren
The current code in reserve_noncached() has two issues: 1) The first update of gd->start_addr_sp always rounds down to a section start. However, the equivalent calculation in cache.c:noncached_init() always first rounds up to a section start, then subtracts a section size. These two calculations differ if the initial value is already rounded to section alignment. 2) The second update of gd->start_addr_sp subtracts exactly CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in cache.c:noncached_init() rounds the noncached size up to section alignment before subtracting it. The two calculations differ if the noncached region size is not a multiple of the MMU section size. In practice, one/both of those issues causes a practical problem on Jetson TX1; U-Boot triggers a synchronous abort during initialization, likely due to overlapping use of some memory region. This change fixes both these issues by duplicating the exact calculations from noncached_init() into reserve_noncached(). However, this fix assumes that gd->start_addr_sp on entry to reserve_noncached() exactly matches mem_malloc_start on entry to noncached_init(). I haven't traced the code to see whether it absolutely guarantees this in all (or indeed any!) cases. Consequently, I added some comments in the hope that this condition will continue to be true. Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area") Cc: Vikas Manocha <vikas.manocha@st.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2019-08-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
2019-08-28MPC8548: dts: Added PCIe DT nodeHou Zhiqiang
MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P5040: dts: Added PCIe DT nodesHou Zhiqiang
P5040 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P4080: dts: Added PCIe DT nodesHou Zhiqiang
P4080 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
generated by cgit (git 2.34.1) at 2024-12-29 17:29:30 +0000