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2018-07-19lib: fdtdec: Rename routine fdtdec_setup_memory_size()Siva Durga Prasad Paladugu
This patch renames the routine fdtdec_setup_memory_size() to fdtdec_setup_mem_size_base() as it now fills the mem base as well along with size. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-19microblaze: Do not force saving variables to flashMichal Simek
There is no reason to save variables to flash only. Select option via Kconfig instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19microblaze: Convert generic platform to DM gpioMichal Simek
Converting GPIO to DM requires to do changes in reset subsystem that's why support for Microblaze soft reset via sysreset and GPIO sysreset support was added. These two patches enables enabling GPIO DM. Microblaze soft reset is bind at last reset method. GPIO reset is handled via sysreset with adding this fragment to DT. gpio-restart { compatible = "gpio-restart"; gpios = <&reset_gpio 0 0 0>; /* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */ }; hard-reset-gpio property is not documented and also handled. Conversion is required. Unfortunately do_reset is required for SPL that's why use only soft microblaze reset for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19arm64: xilinx: Setup default number of chipselects for zcu100Michal Simek
There is only one chipselect on each connector. Define it directly in board dts file. There should be an option to use more chipselects via gpios. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19microblaze: Cosmetic changes in Microblaze related filesShreenidhi Shedi
Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19microblaze: Do not call timer init that earlyMichal Simek
Timer needs to be converted to DM but as of now it can't be called so early because intc controller is not ready. Call it later in board_r.c. Before this patch timer_init is called twice which is wrong. The patch is blocking initialization before relocation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19microblaze: Use default implementation from include/linux/io.hMichal Simek
There is no reason not to use default ioremap/iounmap io functions. The patch remove Microblaze macros. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variableLuca Ceresoli
U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on ZynqMP (PS init for short). The current logic to locate this file for both platforms is: 1. if a board-specific file exists in board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c then use it 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c In the latter case the file does not exist in the U-Boot sources and must be copied in the source tree from the outside before starting the build. This is typical when it is generated from Xilinx tools while developing a custom hardware. However making sure that a board-specific file is _not_ found (and used) requires some trickery such as removing or overwriting all PS init files (e.g.: the current meta-xilinx yocto layer). This generates a few problems: * if the source tree is shared among different out-of-tree builds, they will pollute (and potentially corrupt) each other * the source tree cannot be read-only * any buildsystem must add a command to copy the PS init file binary * overwriting or deleting files in the source tree is ugly as hell Simplify usage by allowing to pass the path to the desired PS init file in kconfig variable XILINX_PS_INIT_FILE. It can be an absolute path or relative to $(srctree). If the variable is set, the user-specified file will always be used without being copied around. If the the variable is left empty, for backward compatibility fall back to the old behaviour. Since the issue is the same for Zynq and ZynqMP, add one kconfig variable in a common place and use it for both. Also use the new kconfig help text to document all the ways to give U-Boot the PS init file. Build-tested with all combinations of: - platform: zynq or zynqmp - PS init file: from XILINX_PS_INIT_FILE (absolute, relative path, non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/ - building in-tree, in subdir, in other directory Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-07-17sunxi: Enable eMMC on Libre Computer Board ALL-H3-CC boardsChen-Yu Tsai
The Libretech ALL-H3-CC has a high density connector for attaching an eMMC module. The module form factor and connection is specific to Libretech, and has provisions for split vmmc/vqmmc (core and I/O) voltage supplies, but this board does not wire the vqmmc side. The H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either. Only 3.3V is supported. A specific module that ties vqmmc to vmmc, with both at 3.3V, must be used. Given that a) eMMC is not designed to be hotplugged, b) power is always provided on the pins, and c) MMC controllers can deal with missing cards, we can enable this by default. If a module is attached it will be picked up by the system. The device tree change was also submitted to the Linux Kernel and has already been queued up for 4.19. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boardsSiva Durga Prasad Paladugu
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16configs: Bananapi_M2_Ultra: enable gigabit ethernetLothar Felten
Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40) Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16sunxi: R40: add gigabit ethernet devicetree nodeLothar Felten
Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins. Updated to match the Linux kernel's device tree. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16sunxi: R40: add gigabit ethernet clocksLothar Felten
Add clock control entries for the gigabit interface of the Allwinner R40/V40 CPU Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16dm: sunxi: Use DM for MMC and SATA on all A10 boardsAdam Sampson
Use the driver model for MMC and SATA, in preparation for CONFIG_BLK defaulting to y. Tested on A10 Cubieboard. Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2018-07-16sunxi: DT: A64: add proper SoPine baseboard device treeAndre Przywara
When the defconfig for the SoPine baseboard was added, there wasn't any proper DT for the board yet, so we used the Pine64 DT as a placeholder. Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use them in our defconfig. This is as of v4.18-rc3, exactly Linux commit: commit 7d556bfc49adddf2beb0d16c91945c3b8b783282 Author: Jagan Teki <jagannadh.teki@gmail.com> Date: Mon Dec 4 10:23:07 2017 +0530 arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: H3: update board .dts files from LinuxAndre Przywara
Update the .dts file for the various boards with an Allwinner H3 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 721afaa2aeb860067decdddadc84ed16f42f2048 (HEAD) Merge: 7c00e8ae041b 87815dda5593 Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Mon Jun 11 17:57:38 2018 -0700 Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc This also includes the OrangePi Zero .dts, which technically has an Allwinner H2+ SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: H5: update board .dts files from LinuxAndre Przywara
Update the .dts file for the various boards with an Allwinner H5 SoC. This is as of v4.18-rc3, exactly Linux commit: commit af5d05bdc99c211729cba0a3d5417bccfa308caf Author: Neil Armstrong <narmstrong@baylibre.com> Date: Tue Apr 24 13:47:14 2018 +0200 arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: update device tree files for Allwinner H3 and H5 SoCsAndre Przywara
Update the device tree files from the Linux tree as of v4.18-rc3, exactly Linux commit: commit 55c5ba5e49a0a124ed416880e8227b493474495e Author: Chen-Yu Tsai <wens@csie.org> Date: Tue Apr 24 19:34:22 2018 +0800 arm64: dts: allwinner: h5: Add cpu0 label for first cpu Since the H3 and H5 are very similar (aside from the actual ARM cores), they share most the SoC .dtsi and thus have to be updated together. One tiny change is the removal of the "arm/" prefix from the include path in the sun50i-h5.dtsi, which is needed because we don't share the same sophisticated DT directory layout of Linux. Also we need to fix up the board .dts files already, since the .dtsi removes some pins, so the .dts can't reference them anymore. This is to maintain bisectability. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: A64: update board .dts files from LinuxAndre Przywara
Update the .dts files for the various boards with an Allwinner A64 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 818668055c9d588c9a9d151e3b258ed1adacba0b Author: Jagan Teki <jagan@amarulasolutions.com> Date: Mon Apr 23 12:02:39 2018 +0530 arm64: dts: allwinner: a64: bananapi-m64: add usb otg It updates the existing DT files, adds the newly added axp803.dtsi and removes our temporary kludge file to get Ethernet support in U-Boot. I left the amarula-relic alone, as this DT has not reached mainline yet. The changes are not critical anyway, and the next sync will fix this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: A64: update device tree file for Allwinner A64 SoCAndre Przywara
Updates the device tree file from the the Linux tree as of v4.18-rc3, exactly Linux commit: commit c1cff65f9b16b31e731e2e75bbe06638c86e1996 Author: Harald Geyer <harald@ccbib.org> Date: Thu Mar 15 16:25:08 2018 +0000 arm64: dts: allwinner: a64: add simplefb for A64 SoC This also pulls in the newly required include files for the clock and reset bindings, also removes the now redundant part from our *-u-boot.dtsi overlay file. I kept the PWM node from U-Boot, as we recently gained this explicitly for U-Boot's own usage and I don't want to regress here. This node is in the queue for mainline Linux already, so the next sync will make it all equal again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-13mach-stm32: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan
CONFIG_SPL_RESET_SUPPORT has been renamed to CONFIG_SPL_DM_RESET, update this Kconfig file. Fixes: bfc6bae8fa1f ("reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-13Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-12arm: socfpga: Fixes: include <debug_uart.h>Ley Foon Tan
Fix compilation warning when enable CONFIG_DEBUG_UART. arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’: arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration] debug_uart_init(); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit onlyLey Foon Tan
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: dts: socfpga: stratix10: Fix memory nodeLey Foon Tan
Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12imx_lpi2c: Update lpi2c driver to support imx8Ye Li
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory to u-boot include directory as a common header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12ARM: socfpga: Assure correct ACTLR configurationMarek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ARM: socfpga: Make DRAM node available in SPLMarek Vasut
The SPL can also parse the DRAM configuration node to figure out the memory layout, make sure it is available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ARM: socfpga: Pull DRAM size from DTMarek Vasut
Pull the DRAM size from DT instead of hardcoding it into U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan
Add do_bridge_reset() function for Arria 10, it is required by misc.c. arch/arm/mach-socfpga/built-in.o: In function `do_bridge': arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' make[1]: *** [u-boot] Error 1 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan
Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan
Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan
Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Restructure the SPL fileLey Foon Tan
Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan
Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan
Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan
Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan
Move bridge command to misc common driver, in preparation to used by other platforms. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-10board: arm: Add support for Broadcom BCM7445Thomas Fitzsimmons
Add support for loading U-Boot on the Broadcom 7445 SoC. This port assumes Broadcom's BOLT bootloader is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader, loaded as an ELF program by BOLT. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Florian Fainelli <f.fainelli@gmail.com>
2018-07-10configs: Remove empty #ifdef/#ifndef blocks from configsAlex Kiernan
Remove empty #ifdef/#ifndef..#endif blocks where the configuration they guarded has been completely removed. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-07-09reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan
Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET, so can use CONFIG_IS_ENABLED(DM_RESET) checking in reset.h later. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-09arm: dts: bubblegum_96: Enable UART5 for serial consoleManivannan Sadhasivam
This commit enables UART5 found in S900 SoC for serial console support. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09arm: dts: s900: Add UART nodeManivannan Sadhasivam
This commit adds UART node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09clk: Add Actions Semi OWL clock supportManivannan Sadhasivam
This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-09arm: dts: s900: Add Clock Management Unit (CMU) nodesManivannan Sadhasivam
This commit adds Clock Management Unit (CMU) nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09board: Add uCRobotics Bubblegum-96 board supportManivannan Sadhasivam
This commit adds uCRobotics Bubblegum-96 board support. This board is one of the 96Boards Consumer Edition platform based on Actions Semi S900 SoC. Features: - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) - 2GiB RAM - 8GiB eMMC, uSD slot - WiFi, Bluetooth and GPS module - 2x Host, 1x Device USB port - HDMI - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons U-Boot will be loaded by ATF at EL2 execution level. Relevant driver support will be added in further commits. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09arm: Add support for Actions Semi OWL SoC familyManivannan Sadhasivam
This commit adds Actions Semi OWL SoC family support with S900 as the first target SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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