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2011-05-18avr32: use single linker scriptAndreas Bießmann
This patch move the atstk100x linker script to $(CPUDIR) and delete other pure copies of this file in each board directory. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18avr32/config.mk: simplify PLATFORM_RELFLAGSAndreas Bießmann
This patch removes PLATFORM_RELFLAGS from board specific config.mk files and define them in arch specific config.mk file. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18avr32: fix linkingAndreas Bießmann
This patch fixes following error: ---8<--- avr32-linux-ld: --gc-sections and -r may not be used together --->8--- Since 8aba9dceebb14144e07d19593111ee3a999c37fc all avr32 boards are broken due to linking error as seen above. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18at91: fixed at91sam9263 system fileDaniel Gorsulowski
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2011-05-18remove __attribute__ ((packed)) in at91 headersJens Scharsig
* remove __attribute__ ((packed)) to prevent byte access to soc registers in some gcc version Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2011-05-18at91rm9200: fix lowlevel_init() SMRDATA sizeJens Scharsig
* use start/end label for initialization tables instead of fix values Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-05-18AT91: fix timer.c - remove reset_timer()Reinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: remove LEGACY from at91_rstc.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: change includes from asm/arch/io.h to asm/io.hReinhard Meyer
and remove the now unused asm/arch-at91/io.h Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: cleanup at91sam9260_matrix.h to struct SoC accessReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: fix related at91 system/driver filesReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: fix related arch-at91 header filesReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: cleanup hardware.h, remove memory-map.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: rework at91sam9g45.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: rework at91sam9263.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: rework at91sam9261.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18AT91: rework at91sam9260.hReinhard Meyer
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18avr32: fixup definitions to ATMEL_BASE_xxxAndreas Bießmann
Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18avr32: rename memory-map.h -> hardware.hAndreas Bießmann
Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-13powerpc/mpc8xxx: reword max tCKmin messageYork Sun
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-13powerpc/85xx: fix compatible property for the L2 cache nodeTimur Tabi
The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-12Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2011-05-12PPC405EX CHIP_21 erratumSteven A. Falco
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
2011-05-11Kirkwood: allow to override CONFIG_SYS_TCLKSimon Guinot
This patch allow to override CONFIG_SYS_TCLK from board configuration files. This is needed for the Network Space v2 which use a non standard core clock frequency (166MHz instead of 200MHz for a 6281 SoC). As a possible enhancement for 6281 and 6282 devices, TCLK could be dynamically detected by checking the Sample at Reset register bit 21. Additionally this patch fix a typo. Signed-off-by: Simon Guinot <sguinot@lacie.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
2011-05-11MX31: change return value of get_cpu_revStefano Babic
Drop warnings in get_cpu_rev and changes the return value (a u32 instead of char * is returned) of the function to be coherent with other processors. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Detlev Zundel <dzu@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-11MX31: removed warning due to missing prototypeStefano Babic
Drop warning caused by missing prototype for mxc_hw_watchdog_reset(). Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-05-10Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk
2011-05-10Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2011-05-10MIPS: Move timer code to arch/mips/cpu/$(CPU)/Shinya Kuribayashi
Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-10MIPS: Introduce --gc-sections for MIPSDaniel Schwierzeck
All architectures but MIPS are using --gc-sections on final linking. This patch introduces that feature for MIPS to reduce the memory and flash footprint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-07MIPS: Coding style cleanups on common assembly filesShinya Kuribayashi
Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-07MIPS: Remove mips_cache_lock() featureShinya Kuribayashi
As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS] Request for the 'mips_cache_lock()' removal), such feature is no longer needed for current MIPS implementation of U-Boot, and no one in the tree uses it for years. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-04-30Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2011-04-30Handle most LDSCRIPT setting centrallyScott Wood
Currently, some linker scripts are found by common code in config.mk. Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is sometimes in arch config.mk and sometimes in board config.mk. Some are found using an arch-specific rule for looking in CPUDIR, etc. Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds. Replace all of this -- except for a handful of boards that are actually selecting a linker script in a unique way -- with centralized ldscript finding. If board code specifies LDSCRIPT, that will be used. Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used. If neither of these are specified, then the central config.mk will check for the existence of the following, in order: $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds $(TOPDIR)/$(CPUDIR)/u-boot.lds Some boards (sc3, cm5200, munices) provided their own u-boot.lds that were dead code, because they were overridden by a CPUDIR u-boot.lds under the old powerpc rules. These boards' own u-boot.lds have bitrotted and no longer work -- these lds files have been removed. Signed-off-by: Scott Wood <scottwood@freescale.com> Tested-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-30mpc832x: add support for the mpc8321 based suvd3 boardHeiko Schocher
- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2011-04-29fsl-ddr: Fix mixed-case macro namesKyle Moffett
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc: eSPI and eSPI controller supportMingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi
Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi
The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc: use 'video-mode' environment variable to configure DIUTimur Tabi
Use the 'video-mode' environment variable (for Freescale chips that have a DIU display controller) to designate the full video configuration. Previously, the DIU driver used the 'monitor' variable, and it was used only to determine the output video port. The old definition of the "monitor" environment variable only determines which video port to use for output. This variable was set to a number (0, 1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port. The resolution was hard-coded into board-specific code. The Linux command-line arguments needed to be hard-coded to the proper video definition string. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-04-27powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock
A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips
versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu
The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang
The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala
The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve
Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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