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2019-11-17arm: dts: rk3399-roc-pc: Sync latest dts changes from LinuxJagan Teki
Few important regulator power rails fixes are available in linux-next, so sync them same. Here is the last commit details: commit <9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails") Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: Init driver otg_data for rk3288 usb phyKever Yang
RK3288 needs to init the otg_data in board level to make the phy driver work. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: usb: Migrate to use ofnodeKever Yang
Migrate to use ofnode_* instead of fdt_* so that we may able to use live dt for usb udc driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add px30 architecture coreHeiko Stuebner
Add core architecture code to support the px30 soc. This includes a separate tpl board file due to very limited sram size as well as a non-dm sdram driver, as this also has to fit into the tiny sram. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add px30 devicetreesHeiko Stuebner
Add px30 related devicetrees synced from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: misc: read cpuid either from efuse or otpHeiko Stuebner
Newer Rockchip socs use a different ip block to handle one-time- programmable memory, so depending on what got enabled get the cpuid from either source. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: add core px30 headersHeiko Stuebner
Add headers needed by the upcoming px30 support, including two new dt-binding headers taken from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17spl: separate SPL_FRAMEWORK config for spl and tplHeiko Stuebner
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all cases, making the TPL bigger. There may be cases where the TPL is really size constrained due to its underlying ram size. Therefore introduce a new TPL_FRAMEWORK option and make the relevant conditionals check for both. The default is set to "y if SPL_FRAMEWORK" to mimic the previous behaviour where the TPL would always get the SPL framework if it was enabled in SPL. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update calculate_strideKever Yang
Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: migrate to use common codeYouMin Chen
For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3328: use common sdram driverYouMin Chen
RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: px30: add sdram driverYouMin Chen
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common msch reg definitionKever Yang
The noc register bit definition may be the same for different SoC while the offset of the register may be different, add the struction definition as common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add phy driver code for PX30Kever Yang
This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add controller code for PX30Kever Yang
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common code for sdram driverKever Yang
There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: update the sys_reg to sys_reg2Kever Yang
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable name to what we real use to avoid confuse people. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: extend to use sys_reg3 for capacity infoKever Yang
Since we have new DRAM type and to support different DRAM size in different CS, we need more bits, so introduce sys_reg3 to record the info. Note that the info in sys_reg3 is extension to sys_reg2 and the info in sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as VERSION2. All the ENC macro are moved to sdram_common.h since the sdram.c only need to do the info decode. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: sdram: move cap structure and debug function to sdram_common.hKever Yang
The sdram.h suppose to be helper file for sdram.c which including dram size decode and some u-boot related dram init interface, and all structure and function for dram driver move to sdram_common.h Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram.h to sdram_rk3288.hKever Yang
The header file sdram.h is used for rk3288 and similar SoCs, rename it to make it more understandable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-12Merge tag 'u-boot-imx-20191105' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
2019-11-11Merge tag 'u-boot-rockchip-20191110' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature.
2019-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI
2019-11-10rockchip: firefly-rk3288: Enable TPL supportKever Yang
This patch enable TPL support for firefly-rk3288 board, which works ths same way with other RK3288 board like Tinker, evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: adding the missing "/" in entries of boot_devicesLevin Du
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work as expected. When board_boot_order() `spl-boot-order.c` meets "same-as-spl", it gets the conf by looking the boot_devices table by boot source, and parse the node by the conf with: node = fdt_path_offset(blob, conf); which will failed without the "/" indicating the path. Currently only entries of boot_devices in rk3399 have the "/" prefix. Therefore add the missing ones in other boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: rk3399: update SPL_STACK_R_ADDRKever Yang
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; default to 0x4000000(64MB) instead of 0x80000(512KB) for this address can support all the SoCs including those may have only 64MB memory, and also reserve enough space for atf, kernel(in falcon mode) loading. After the ATF entry move to 0x40000, the stack from 0x80000 may be override when loading ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: make_fit_atf.py: allow inclusion of a tee binaryHeiko Stuebner
A trusted execution environment should also get loaded as loadable from a fit image, so add the possibility to present a tee.elf to make_fit_atf.py that then gets included as additional loadable into the generated its. For ease of integration the additional loadable is created as atf_(x+1) after all others to re-use core generation loops. Tested against the combinations of 1-part-atf and multi-part-atf each time with and without a tee binary present. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: dts: rk3328: rock64: Add same-as-spl orderEmmanuel Vadot
rk3328 can use same-as-spl option so next loaders are loaded from the same medium. Add the boot order in the rock64 dts otherwise booting from sdcard will result in u-boot looking into the eMMC. Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: rk3399: Add Leez P710 supportAndy Yan
Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-08Merge branch '2019-11-07-master-imports'Tom Rini
- Add Phytium Durian Board - Assorted bugfixes - Allow for make ERR_PTR/PTR_ERR architecture specific
2019-11-08freescale/powerpc: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08freescale/layerscape: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix warning if no hwconfig is definedPankaj Bansal
While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
2019-11-08armv8: fsl-layerscape: introduce fsl_board_late_init()Michael Walle
The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_xMichael Walle
The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls1028a: add erratum A-050382 workaroundLaurentiu Tudor
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: lx2160a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: add missing SATA3 and SATA4 base addressesLaurentiu Tudor
LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls2088a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-layerscape: guard caam specific definesLaurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: do not use layerscape EFI reset if PSCI usedMathew McBride
If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: dts: ls1088a: add PSCI binding for LS1088AMathew McBride
This allows the use of PSCI calls to trusted firmware to initiate reset and poweroff events with CONFIG_PSCI_RESET and CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target board has implemented a custom reset or poweroff procedure in EL3. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-07ARM: dts: logicpd-som-lv-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supplyKeerthy
Hook buck12_reg to vtm avs supply Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 nodeKeerthy
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support Signed-off-by: Keerthy <j-keerthy@ti.com>
generated by cgit (git 2.34.1) at 2024-12-25 19:23:33 +0000